Your manager has given you the task of implementing the following pseudo code in an FPGA:

if is_odd(a + d) {

p = (a + d)*2 + ((b + c) - 1)/4;

} else {

p = (b + c)*2 + d;

}

NOTES:

- You must use registers on all input and output ports.
- p, a, b, c, and d are to be implemented as 8-bit signed signals.
- A 2-input 8-bit ALU that supports both addition and subtraction takes 1clock cycle.
- A 2-input 8-bit multiplier or divider takes 4 clock cycles.
- A small amount of additional circuitry (e.g. a NOT gate, an AND gate, or a MUX) can be squeezed into the same clock cycle(s) as an ALU operation, multiply, or divide.
- You can require that the environment provides the inputs in any order and that it holds the input signals at the same value for multiple clock cycles.

- What is the minimum number of clock cycles needed to implement the pseudocode with a circuit that has two input ports?
- What is the minimum number of ALUs, multipliers, and dividers needed to achieve the minimum number of clock cycles that you just calculated?
- What is the minimum number of datapath storage registers (8, 6, 4, and 1 bit) and clock cycles needed to implement the pseudocode if the circuit can have at most one ALU, one multiplier, and one divider?

Good luck!!

--

Create your RupeeMail Account & refer your friends to earn launch referral bonus on every new registration.

Try this... http://www.rupeemail.in/rupeemail/invite.do?in=MTUyNjUlIyVSajZ5dlBocDhrU3ozWVZ3bTBhZWQyQ2ZF

--

Create your RupeeMail Account & refer your friends to earn launch referral bonus on every new registration.

Try this... http://www.rupeemail.in/rupeemail/invite.do?in=MTUyNjUlIyVSajZ5dlBocDhrU3ozWVZ3bTBhZWQyQ2ZF

## Post a Comment

Your comments will be moderated before it can appear here.