Displaying posts in the categoryVerilog
Verilog articles
Verilog
To divide a 1 GHz clock down to an average of exactly 622.08 MHz with digital logic only, use a phase accumulator: add 1944 every input cycle, modulo 3125, and produce one output pulse each time the sum wraps. That works because 1000 / 622.08 reduces exactly to 3125 / 1944, so the output alternates between periods of one and two input cycles, the long-run average is exact, and every output edge stays within one input cycle of its ideal position.…
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Murugavel Ganesan
August 29, 2025
Verilog
The most common RTL coding mistakes come from forgetting that Verilog and VHDL describe hardware, not a program. Unsynchronised clock domain crossings, software-style code, accidental latches, incomplete resets, tangled state machines, thin simulation, missing timing constraints, hard-coded widths, unreadable code and unchecked synthesis output account for most of the bugs found in junior engineers' designs. Each one is avoidable with a fe…
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Murugavel Ganesan
June 09, 2025
Verilog
RTL design and micro architecture interviews test three things: whether you can describe hardware correctly in Verilog or SystemVerilog, whether you understand timing, clocking and reset well enough to build something that works on silicon, and whether you can reason about trade-offs in performance, power and area. The 50 questions below cover all three, from counters and FIFOs to pipelines, caches and clock domain crossing, and each one now com…
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Murugavel Ganesan
January 03, 2025
Verilog
X-propagation is the way an unknown value, written as X in Verilog and SystemVerilog, spreads from its source through the logic of a design during simulation. The danger is that RTL simulation handles X inconsistently: some constructs hide an X and turn it into a clean 0 or 1 (X-optimism), while others turn known values into X (X-pessimism). Optimism can hide real bugs until silicon, and pessimism wastes debug time on failures that real hardware…
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Murugavel Ganesan
January 07, 2024
Verilog
FPGA based cryptographic acceleration means moving encryption, decryption, hashing and signature work from a general-purpose processor into custom logic on a field-programmable gate array. The FPGA wins when the work is regular and highly parallel, such as AES on a 100 Gbit/s link or SHA-256 over a storage stream, because it can pipeline the algorithm and process a new block every clock cycle. It also stays reprogrammable, so the design can foll…
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Murugavel Ganesan
December 12, 2023
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