Hughes Networks Interview Questions

What is setup/hold? What are setup and hold time impacts on timing? How will you fix setup and hold violations?
  • Explain function of Muxed FF (Multiplexed Flip Flop) /scan FF (Scal Flip Flop).
  • What are tested in DFT (Design for Testability)?
  • In equivalence checking, how do you handle scanen signal?
  • In terms of CMOS (Complimentary Metal Oxide Semiconductor), explain physical parameters that affect the propagation delay?
  • What are power dissipation components? How do you reduce them?
Answer:
Short Circuit Power
Leakage Power Trends
Dynamic Power
Low Power Design Techniques

  • How delay affected by PVT (Process-Voltage-Temperature)?
Answer: Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis (STA)
  • Why is power signal routed in top metal layers?
Source:
http://vlsifaq.blogspot.com/


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