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In building the timing constraints, do you need to constrain all IO (Input-Output) ports?
Yes, it is important to constrain all input and output (I/O) ports when building timing constraints for a design. I/O constraints, also commonly referred to as pin assignments, are used to assign a signal to a specific I/O (pin) or I/O bank. These constraints may also be used to specify the user-configurable I/O characteristics for individual I/Os and I/O banks. Timing constraints are used to specify the timing characteristics of the design, and it is important to include complete I/O timing constraints in order to achieve PCB-level timing convergence. This ensures that the interface with the outer world is reliable and that each signal arrives reliably to the relevant flip-flop on the FPGA3.
Can a single port have multi-clocked? How do you set delays for such ports?
Yes, a single port can have multiple clocks. For example, a port can work with two frequencies (regular and divided by 2 of the regular).
How is scan DEF (Design Exchange Format) generated?
Scan DEF (Design Exchange Format) is a file that contains the scan chain connectivity information, which is also present in the netlist. Some EDA tools let us auto-trace the scan chains (without annotating with SCANDEF), given the information on SCAN in/out points. However, there is additional information present in the SCANDEF file, which makes it easier to map or annotate scan chains. For example, when there are multi-input components in the scan chain, tracing the scan chain becomes difficult. Also, it is not possible to define PARTITION information about scan chains (Scan Flops can be swapped across chains with the same PARTITION). These advantages of using SCANDEF make it preferred over auto-tracing of the scan chains.
What is purpose of lockup latch in scan chain?
A lock-up latch is a transparent latch used intelligently in places where clock skew is very large and meeting hold timing is a challenge due to large uncommon clock paths. Lock-up latches are necessary to avoid skew problems during the shift phase of scan-based testing. They are used to connect two flops in a scan chain having excessive clock skews/uncommon clock paths as the probability of hold failure is high in such cases. For example, the launching and capturing flops may belong to two different domains. Functionally, they might not be interacting. Hence, the clock of these two domains will not be balanced and will have a large uncommon path. But in scan-shift mode, these interact shifting the data in and out. Had there been no lockup latches, it would have been very difficult for STA engineer to close timing in a scan chain across domains. Also, the probability of chip failure would have been high as there is a large uncommon path between the clocks of the two flops leading to large on-chip-variations. That is why lockup latches can be referred to as the soul mate of scan-based designs.
Explain short circuit current!
In the context of VLSI, short circuit current refers to a momentary current that flows when both nMOS and pMOS networks may be momentarily ON at once during transistor switching. This leads to a blip of “short circuit” current. Short circuit current is generally less than 10% of dynamic power if rise/fall times are comparable for input and output.
What are the pros and cons of using different Vt cells?
In VLSI design, using different threshold voltage (Vt) cells can help balance power and timing. By changing the characteristics like doping of the channels, threshold voltages can be varied. There are commonly three types of Vt cells available: LVT (Low-Vt), SVT (Standard-Vt), and HVT (High-Vt).
LVT cells have a lowered threshold voltage, which means they have faster operation, but also higher leakage currents.
SVT cells are optimized for power and timing, so they have medium leakage and are faster than HVT cells.
HVT cells have the highest threshold voltage for device operation in this group. The cells are slower, but due to the higher threshold, leakage is also lower.
Ultra-low Vt (threshold voltage) cells have a very low threshold voltage. This means that they can turn on at a lower voltage than standard transistors, allowing for faster switching speeds and lower power consumption. However, ultra-low Vt cells also have higher leakage currents, which can increase static power consumption. As a result, designers must carefully balance the use of ultra-low Vt cells with other types of transistors to achieve the desired performance and power characteristics for their design.
In timing critical paths, LVT cells can be used to take advantage of their higher performance. One important point to note is that you need to use the same threshold cells for the clock tree to reduce variations in the clock tree. You can decide on the timing/power requirement of the design, but a standard practice is to reserve SVT cells for clock trees. Different Vt versions of the same functional cell usually have the same footprint, so the cells can be swapped interchangeably and easily during layout. However, the timing impact of using different Vt cells has to be taken into account during cell swapping. The implementation tool also usually handles this analysis automatically.
How do you set inter clock uncertainty?
Inter-clock uncertainty is a measure of the uncertainty between two clocks in a design. It is used to account for clock skew and jitter between the two clocks. To set inter-clock uncertainty, you can use the “set_clock_uncertainty” command in your synthesis or static timing analysis (STA) tool. This command allows you to specify the amount of uncertainty between two clocks, either as an absolute value or as a percentage of the clock period. For example, to set an inter-clock uncertainty of 500ps between clock1 and clock2, you can use the following command: set_clock_uncertainty -inter 500 [get_clocks clock1] [get_clocks clock2]. Is there anything else you would like to know?
In Design Compiler, how do you constrain clocks, IO (Input-Output) ports, maxcap, max tran?
In Synopsys Design Compiler (DC), you can constrain clocks, I/O ports, maximum capacitance (maxcap), and maximum transition time (max_tran) using the following commands:
To create a clock and set its period, use the create_clock command. For example, to create a clock named “clk” with a period of 10ns, you can use the following command: create_clock -period 10 [get_ports clk].
To set input and output delays for I/O ports, use the set_input_delay and set_output_delay commands. For example, to set an input delay of 2ns on port “data_in” with respect to clock “clk”, you can use the following command: set_input_delay -clock clk 2 [get_ports data_in]. Similarly, to set an output delay of 1ns on port “data_out” with respect to clock “clk”, you can use the following command: set_output_delay -clock clk 1 [get_ports data_out].
To set the maximum capacitance for a port or a net, use the set_max_capacitance command. For example, to set the maximum capacitance of port “data_out” to 0.05pF, you can use the following command: set_max_capacitance 0.05 [get_ports data_out].
To set the maximum transition time for a port or a net, use the set_max_transition command. For example, to set the maximum transition time of port “data_out” to 1ns, you can use the following command: set_max_transition 1 [get_ports data_out].
What are differences in clock constraints from pre CTS (Clock Tree Synthesis) to post CTS (Clock Tree Synthesis)?
Clock Tree Synthesis (CTS) is the process of inserting buffers and inverters to balance the clock tree and minimize skew. Before CTS, the clock constraints are used to guide the synthesis tool to meet the timing requirements of the design. The clock period, uncertainty, and latency are specified to ensure that the design meets the required performance. After CTS, the clock tree has been balanced and the skew has been minimized. The clock constraints are updated to reflect the actual characteristics of the clock tree. The clock latency and uncertainty values may be updated based on the results of CTS. The updated constraints are used during post-CTS timing analysis to verify that the design meets the required performance. In summary, before CTS, clock constraints are used to guide the synthesis tool to meet the timing requirements of the design. After CTS, the clock constraints are updated to reflect the actual characteristics of the clock tree and are used during post-CTS timing analysis to verify that the design meets the required performance.
How is clock gating done?
Clock gating is a technique used in digital circuit design to reduce power consumption. It works by disabling the clock signal to portions of a circuit that are not currently in use, effectively stopping their operation and reducing power consumption. Clock gating is typically implemented using a clock gating cell, which is a logic gate that controls the flow of the clock signal to a portion of the circuit. The clock gating cell is controlled by an enable signal, which determines whether the clock signal is allowed to pass through to the downstream circuitry. When the enable signal is asserted, the clock signal is allowed to pass through and the downstream circuitry operates normally. When the enable signal is de-asserted, the clock signal is blocked and the downstream circuitry is effectively disabled. Clock gating can be applied at various levels of granularity, from individual flip-flops to entire blocks of logic. The choice of granularity depends on the specific design and its power consumption requirements.
What constraints you add in CTS (Clock Tree Synthesis) for clock gates?
What is trade off between dynamic power (current) and leakage power (current)?
How do you reduce standby (leakage) power?
Explain top level pin placement flow? What are parameters to decide?
Given block level netlists, timing constraints, libraries, macro LEFs (Layout Exchange Format/Library Exchange Format), how will you start floor planning?
With net length of 1000um how will you compute RC values, using equations/tech file info?
What do noise reports represent?
What does glitch reports contain?
What are CTS (Clock Tree Synthesis) steps in IC compiler?
What do clock constraints file contain?
How to analyze clock tree reports?
What do IR drop Voltagestorm reports represent?
Where /when do you use DCAP (Decoupling Capacitor) cells?
What are various power reduction techniques?
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