Qualcomm Interview Questions

In building the timing constraints, do you need to constrain all IO (Input-Output) ports?

• Can a single port have multi-clocked? How do you set delays for such ports?
• How is scan DEF (Design Exchange Format) generated?
• What is purpose of lockup latch in scan chain?
• Explain short circuit current.

Answer: Short Circuit Power

• What are pros/cons of using low Vt, high Vt cells?

Answer:
Multi Threshold Voltage Technique
Issues With Multi Height Cell Placement in Multi Vt Flow

• How do you set inter clock uncertainty?

Answer:

set_clock_uncertainty –from clock1 -to clock2

• In DC (Design Compiler), how do you constrain clocks, IO (Input-Output) ports, maxcap, max tran?
• What are differences in clock constraints from pre CTS (Clock Tree Synthesis) to post CTS (Clock Tree Synthesis)?

Answer:

Difference in clock uncertainty values; Clocks are propagated in post CTS.

In post CTS clock latency constraint is modified to model clock jitter.

• How is clock gating done?

Answer: Clock Gating

• What constraints you add in CTS (Clock Tree Synthesis) for clock gates?

Answer:

Make the clock gating cells as through pins.

• What is trade off between dynamic power (current) and leakage power (current)?

Answer:
Leakage Power Trends
Dynamic Power

• How do you reduce standby (leakage) power?

Answer: Low Power Design Techniques

• Explain top level pin placement flow? What are parameters to decide?
• Given block level netlists, timing constraints, libraries, macro LEFs (Layout Exchange Format/Library Exchange Format), how will you start floor planning?
• With net length of 1000um how will you compute RC values, using equations/tech file info?
• What do noise reports represent?
• What does glitch reports contain?
• What are CTS (Clock Tree Synthesis) steps in IC compiler?
• What do clock constraints file contain?
• How to analyze clock tree reports?
• What do IR drop Voltagestorm reports represent?
• Where /when do you use DCAP (Decoupling Capacitor) cells?
• What are various power reduction techniques?

Answer: Low Power Design Techniques

Source:
[http://vlsifaq.blogspot.com/]