ST Microelectronics Interview Questions: Physical Design Answers

These are 20 physical design interview questions from an ST Microelectronics interview, covering place and route, clock tree synthesis, static timing analysis under on-chip variation (OCV), ECOs, IR drop, routing grids and the Perl and Tcl scripting that every back-end engineer uses. Each original question is kept as posted and now has a short model answer. Experience questions ("what did you face in your project") have no single right answer, so for those the answer shows how to structure a strong reply.

Key takeaways

• The list is weighted toward physical design sign-off: CTS, OCV-aware STA, IR drop, congestion and ECOs.
• For project questions, answer with a real example: the problem, how you found it, the fix, and the measurable result.
• Know the exact commands for common constraints (multicycle paths, timing derates); interviewers check hands-on experience this way.
• Hold violations cannot be fixed by slowing the clock, which is why a design is never signed off with a real hold violation.

The 20 ST Microelectronics interview questions

The questions below are as originally posted. Answers are new.

1. What were the challenges you faced in physical design, PAR (place and route), FV (Formal Verification)?

Pick one example per area. Typical place and route challenges are congestion around macros, timing closure on a few long paths, and IR drop hotspots. Typical formal verification (logic equivalence checking) challenges are failing compare points after scan insertion, clock gating or register retiming, and constant or merged registers that need mapping guidance. Say how you debugged it and what changed in the flow afterwards.

2. What was the average design cycle time for your designs?

Give your own numbers honestly and split them by phase: netlist to first placement, CTS, routing, and the sign-off and ECO loop. Interviewers use this to judge the size and complexity of designs you have handled, so mention gate count, clock frequency and process node with it.

3. What part are your areas of interest in physical design?

Name one or two areas (for example floorplanning and power planning, CTS, or timing closure and sign-off) and back each with a task you did. A focused answer with evidence is stronger than "everything".

4. Explain ECO (Engineering Change Order) methodology used in your projects.

There are two kinds. A timing ECO fixes setup, hold, transition or crosstalk issues found in sign-off STA by sizing cells, inserting or removing buffers, or swapping threshold voltage. A functional ECO implements a logic change late in the flow. A typical functional ECO flow is: change the RTL, generate a netlist patch (by hand or with an automated ECO tool), prove the patched netlist equivalent to the new RTL, place the new cells incrementally (or map them to spare cells for a metal-only ECO), route the changes incrementally, then rerun STA, DRC, LVS and the other sign-off checks.

5. Explain CTS (Clock Tree Synthesis) flow used in your projects.

Inputs are the clock definitions from the SDC file and a CTS specification: target skew, maximum insertion delay, maximum transition, the buffers or inverters allowed, and non-default routing rules for clock nets. The tool builds the tree, balances skew, and respects exceptions such as exclude pins and stop pins. After CTS, clocks are switched to propagated mode, hold violations are fixed, and clock nets are routed early with shielding or wider spacing. The clock tree synthesis post on this blog explains the basics.

6. What kind of routing issues did you face in your projects? Mention the recent one?

Common issues are DRC shorts and spacing violations in congested regions, pin access problems on dense standard cells, antenna violations, and crosstalk on long parallel nets. A good reply names one, gives the root cause (for example a macro channel that was too narrow) and the fix (channel widening, placement blockages, layer promotion, or diode insertion for antennas).

7. How does STA (Static Timing Analysis) in OCV (On Chip Variation) conditions done?

OCV analysis assumes that cells and wires on the same die can be faster or slower than the library corner. For a setup check, the launch clock path and data path are timed late (slowed by a derate such as 1.05) and the capture clock path early (for example 0.95). For a hold check it is the reverse. Because this pessimism also applies to the clock path shared by launch and capture, clock reconvergence pessimism removal (CRPR) credits back the difference on the common part. Advanced methods (AOCV, POCV) replace a flat derate with derates that depend on path depth and distance, or with statistical values. See advanced on-chip variation (OCV) in PrimeTime.

8. How do you set OCV (On Chip Variation) in the tool you used?

In Synopsys PrimeTime, select OCV analysis with set_operating_conditions -analysis_type on_chip_variation, apply derates with set_timing_derate -early 0.95 and set_timing_derate -late 1.05 (options such as -clock, -data, -cell_delay and -net_delay narrow the scope), and enable CRPR with set timing_remove_clock_reconvergence_pessimism true. The derate values come from the foundry or the library team, not from the designer.

9. How is timing correlation done before and after place and route?

Compare the same paths with the same constraints at each stage: synthesis (wire load or physical estimates), post-placement (estimated routes) and post-route (extracted parasitics in SPEF read by the sign-off STA tool). Look at slack deltas on the worst paths and their causes: detours, crosstalk, wrong RC estimates or different derates. Then tune margins or extraction settings in the implementation tool so its timing tracks sign-off closely.

10. If there are too many pins of the logic cells in one place within core, what kind of issues would you face and how will you resolve?

High pin density causes local routing congestion, DRC violations, detours that hurt timing, and sometimes crosstalk. Fixes include cell padding or keep-out margins, partial placement blockages to cap local density, spreading cells, using cells with better pin access, and floorplan changes that move the logic away from macro corners.

11. Define hash/ @array in perl.

An array (@array) is an ordered list indexed by integers from 0: my @a = (10, 20, 30); print $a[1]; prints 20. A hash (%hash) maps string keys to values: my %cap = (inv => 1.2, nand2 => 1.8); print $cap{nand2}; prints 1.8. Hashes are ideal for report parsing, for example slack per path group.

12. Using TCL (Tool Command Language, Tickle) how do you set variables?

With set: set period 2.5, then read it with $period, for example puts "Period is $period". Lists use set cells [list u1 u2 u3], arrays use set slack(core_clk) -0.05, and command results are captured with brackets: set n [llength $cells].

13. What is ICC (IC Compiler) command for setting derate factor/ command to perform physical synthesis?

The derate command is set_timing_derate, the same as in PrimeTime. Placement with optimisation (physical synthesis inside IC Compiler) is run with place_opt. Synopsys Design Compiler in topographical mode also performs physical-aware synthesis with compile_ultra. Note (November 2026): IC Compiler has since been succeeded by IC Compiler II, which also uses place_opt.

14. What are nanoroute options for search and repair?

NanoRoute is the router in Cadence Encounter (now Innovus). Detailed routing runs search-and-repair iterations that rip up and reroute nets with DRC violations. Options are set with setNanoRouteMode; the ones usually discussed are the number of detailed routing iterations, timing-driven and SI-driven routing, and antenna fixing. Mention the options you actually used and why, for example raising the iteration limit on a congested block.

15. What were your design skew/insertion delay targets?

State your real targets and how they were chosen. Skew targets are usually set as a small fraction of the clock period after allowing for uncertainty, and insertion delay is kept low because a longer clock tree accumulates more OCV pessimism and more power. Mention any useful skew you allowed.

16. How is IR drop analysis done? What are various statistics available in reports?

Static IR analysis uses average current per cell over the power grid resistance. Dynamic analysis uses switching activity (vectorless or from simulation vectors) to find transient drops. Reports typically give worst drop per instance as a voltage and a percentage of supply, voltage and current density maps, electromigration violations, effective resistance to the bumps or pads, and decoupling capacitance coverage.

17. Explain pin density/ cell density issues, hotspots?

Cell density is the fraction of placeable area used; pin density is pins per unit area. A hotspot is a region where either is much higher than the average, giving congestion, IR drop and thermal concentration even when the overall utilisation looks fine. Treat them with density screens, padding, spreading and floorplan changes, as in question 10.

18. How will you relate routing grid with manufacturing grid and judge if the routing grid is set correctly?

The manufacturing grid is the smallest unit on which all mask geometry must sit. Routing track pitches and offsets must be integer multiples of it and must match the pitch in the technology LEF, which is set so that minimum-width wires on adjacent tracks meet minimum spacing. Check that standard cell pins line up with tracks, that track offsets are on the manufacturing grid, and that the router reports no off-grid violations.

19. What is the command for setting multi cycle path?

set_multicycle_path 2 -setup -from [get_cells reg_a] -to [get_cells reg_b], normally paired with set_multicycle_path 1 -hold -from [get_cells reg_a] -to [get_cells reg_b] so the hold check moves back to the original edge. More detail is in multi-cycle paths and false paths in STA.

20. If hold violation exists in design, is it OK to sign off design? If not, why?

No. A hold check compares data and clock arriving at the same edge, so it does not depend on clock period. A real hold violation makes the chip fail at every frequency, and slowing the clock cannot recover it. The only acceptable exceptions are paths proven false or properly constrained (for example asynchronous or static signals with correct exceptions).

Source:
[http://vlsifaq.blogspot.com/]
Raj - Sequence Design

How interviewers extend these questions

• After OCV: "Why does CRPR exist, and what happens to it when the launch and capture clocks are different?"
• After hold sign-off: "Your hold fix created a setup violation. What now?"
• After ECO: "How do you do a metal-only ECO, and what are spare cells?"
• After IR drop: "How does IR drop affect timing, and how do you include it in STA?"

For a companion set focused on timing closure, SDF and SPEF flows and MMMC analysis, see the Texas Instruments (TI) interview questions with answers. Short definitions of these terms are in the Semiconductor Hub glossary entries for on-chip variation (OCV) and clock tree synthesis (CTS).

Frequently asked questions

What does ST Microelectronics ask in physical design interviews?

This list, from an ST Microelectronics interview, focuses on project experience, CTS, OCV-aware STA, ECO flow, IR drop, routing and scripting in Perl and Tcl. Expect follow-ups on whatever you claim in your answers.

Is a hold violation worse than a setup violation?

Yes, in the sense that a setup violation can be traded for a lower clock frequency, while a hold violation fails at any frequency.

What is the difference between OCV, AOCV and POCV?

OCV applies flat early and late derates. AOCV makes the derate depend on logic depth and distance. POCV models each delay statistically with a mean and sigma.

Which scripting languages should a physical design engineer know?

Tcl is essential because EDA tools are driven by it. Perl or Python is used for report parsing and flow automation.

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