Texas Instruments (TI) Interview Questions on Timing with Answers

These seven Texas Instruments (TI) interview questions focus on timing: how constraints are written, how timing closure works, SDF and SPEF back annotation, multi-mode multi-corner (MMMC) STA in PrimeTime, clock gating issues, synthesis strategies for timing and the ECO flow on a routed database. Each original question is kept as posted and now has a model answer you can adapt to your own project experience.

Key takeaways

• Every question here is about getting a design to meet timing and staying correct while doing so.
• Good answers describe a flow in order (inputs, steps, checks, outputs) and name the files involved: SDC, SPEF, SDF, Liberty and the netlist.
• Multi-mode multi-corner analysis means checking every combination of operating mode and PVT corner that matters, each with its own constraints and derates.
• An ECO is only finished when it passes equivalence checking, STA, and physical verification again.

The seven Texas Instruments interview questions

The questions are as originally posted. Answers are new.

1. How are timing constraints developed?

Constraints start from the specification and the micro-architecture, and are written in SDC:

• Clocks: create_clock for each primary clock, create_generated_clock for divided or muxed clocks, plus uncertainty, latency and transition.
• Interfaces: set_input_delay and set_output_delay from the timing budget agreed with the neighbouring block or the board, plus driving cells and loads.
• Exceptions: false paths (for example between asynchronous clocks that use synchronisers) and multicycle paths, each justified by the designer.
• Design rules: maximum transition, capacitance and fanout.
• Modes: separate constraint sets for functional, scan shift, scan capture and other modes.

Constraints are then checked with a constraint linting tool and reviewed with the RTL owners, because an incorrect exception hides real failures.

2. Explain timing closure flow/methodology/issues/fixes.

Flow: synthesis with realistic constraints, floorplan, placement with optimisation, CTS, post-CTS optimisation including hold fixing, routing, post-route optimisation, then sign-off STA with extracted parasitics across all modes and corners, followed by ECO loops until clean.

Setup fixes: upsize cells, swap to lower threshold voltage cells, buffer long nets, restructure logic, move cells closer, use useful skew, or change the RTL (pipelining, retiming).

Hold fixes: insert delay cells or buffers on the data path, downsize, or swap to higher threshold voltage, while watching that setup still passes.

Typical issues: poor correlation between implementation and sign-off timing, congestion that forces detours, crosstalk delay, and setup and hold fixes that fight each other at different corners. The setup and hold time explainer covers the underlying checks.

3. Explain SDF (Standard Delay Format) back annotation/ SPEF (Standard Parasitic Exchange Format) timing correlation flow.

After routing, an extraction tool writes the wire resistance and capacitance of every net to a SPEF file. The STA tool reads the netlist, Liberty libraries and SPEF to compute cell and net delays. From the same data, it can write an SDF file containing those delays, which is annotated into gate-level simulation (for example with $sdf_annotate in Verilog) so the simulation runs with real timing. Correlation means checking that the delays in simulation, the implementation tool and sign-off STA agree: use the same SPEF, the same corner and the same libraries, and compare slack on a set of key paths. See the interview on gate-level simulation (GLS) for how SDF-annotated simulation is used.

4. Given a timing path in multi-mode multi-corner, how is STA (Static Timing Analysis) performed in order to meet timing in both modes and corners, how are PVT (Process-Voltage-Temperature)/derate factors decided and set in the Primetime flow?

Each scenario is one mode (with its own SDC) combined with one corner (a library set at a given process, voltage and temperature, plus an RC extraction corner). The path must meet setup in the slow corners and hold in the fast corners of every mode in which it is active. PrimeTime can run scenarios one by one or together with distributed multi-scenario analysis, and fixes are chosen so they help the failing scenario without breaking another.

Corners come from the foundry and the product specification (for example slow process, low voltage for setup; fast process, high voltage for hold; and both temperature extremes, because at advanced nodes the slowest corner may be at low temperature). Derates come from the foundry or library team as flat OCV values or AOCV/POCV tables. In PrimeTime they are applied per scenario with set_timing_derate (early and late, cell and net, clock and data) or by loading the AOCV or POCV data.

5. With respect to clock gate, what are various issues you faced at various stages in the physical design flow?

• Synthesis: integrated clock gating (ICG) cells are inserted for registers with a common enable; the enable path must meet the clock gating setup check.
• Placement: an ICG placed far from its registers lengthens the gated clock net; an ICG placed far from the clock source makes the enable timing harder.
• CTS: the ICG sits inside the clock tree, so its output clock arrives earlier than the register clocks it drives. The enable path therefore has less time, which is the most common clock gating timing issue. Cloning or merging ICGs helps balance this.
• DFT: a test enable must force the gate open during scan.
• Verification: equivalence checking needs to recognise the inserted gates.

A short definition is in the Semiconductor Hub glossary entry on clock gating.

6. What are synthesis strategies to optimize timing?

Start with correct and complete constraints. Then: use high-effort or ultra compile, enable register retiming where allowed, group critical paths into separate path groups with a critical range, allow boundary optimisation and ungrouping across hierarchy, duplicate registers that drive high fanout, use lower threshold voltage cells on critical paths only, and use physical-aware (topographical) synthesis so wire delays are realistic. If the logic depth is simply too large, change the RTL.

7. Explain ECO (Engineering Change Order) implementation flow. Given post routed database and functional fixes, how will you take it to implement ECO (Engineering Change Order) and what physical and functional checks you need to perform?

1. Update the RTL with the fix and verify it in simulation.
2. Create a netlist patch, by hand for small changes or with an automated ECO tool, and apply it to the post-route netlist.
3. Prove the patched netlist equivalent to the new RTL with logic equivalence checking.
4. Implement physically: incremental placement of new cells and incremental routing for a full-layer ECO, or remapping onto spare cells with metal changes only for a metal-only ECO.
5. Run the checks: STA in all scenarios including SI, DRC, LVS, antenna, IR drop and electromigration, power intent (UPF) checks if the design has power domains, scan chain integrity, and gate-level simulation of the changed logic.

Source:
http://vlsifaq.blogspot.com/

How interviewers extend these questions

• "A path passes in the slow corner but fails hold in the fast corner after your setup fix. What do you do?"
• "Why can the clock gating check be the critical path even though the logic is small?"
• "What is the difference between a full-layer ECO and a metal-only ECO, and when do you choose each?"
• "Why might SDF-annotated simulation pass when STA fails, or the other way round?"

Frequently asked questions

What topics does Texas Instruments ask in VLSI timing interviews?

This list, from a TI interview, covers constraint development, timing closure, SDF and SPEF flows, MMMC STA in PrimeTime, clock gating and ECOs. Expect follow-ups based on your own projects.

What is the difference between SDF and SPEF?

SPEF holds the extracted resistance and capacitance of the wires. SDF holds calculated delays of cells and nets, usually derived from SPEF and the libraries, for use in timing simulation.

What is a scenario in MMMC analysis?

A combination of one operating mode (its constraints) and one corner (libraries, voltage, temperature and RC extraction).

Why is the clock gating enable path often tight?

The clock gate sits before the clock tree buffers, so its clock arrives earlier than at the registers that launch the enable, leaving less of the period for the enable logic.

For more on how timing sign-off fits in the chip flow, see the Semiconductor Hub glossary entry on static timing analysis (STA), and the companion list of ST Microelectronics physical design interview questions.

Advertise on this Blog and see yourself grow! For more information contact us at onenanometer[at]gmail.com