VITAL and its Origins!

Verilog started out as a proprietary simulator in 1984 and enjoyed considerable success due to its C like syntax. In 1990, Cadence Design Systems made the language public. It became an IEEE standard in 1995. VHDL was developed under contract to the U.S. Department of Defense. It became an IEEE standard in 1987. VHDL has its roots in Ada.

For many years there was intense competition between Verilog and VHDL for mind share and market share. Both languages have their strong points. In the end, most EDA companies came out with simulators that work with both. Early in the language wars it was noted that Verilog had a number of built-in, gate-level primitives. Over the years these had been optimized for performance by Cadence and later by other Verilog vendors. Verilog also had a single defined method of reading timing into a simulation from an external file. VHDL, on the other hand, was designed for a higher level of abstraction. Although it could model almost anything Verilog could, and without primitives, it allowed things to be modeled in a multitude of ways. This made performance optimization or acceleration impractical. VHDL was not successfully competing with Verilog as a sign-off ASIC language. The EDA companies backing VHDL saw they had to do something. The something was named VITAL, the VHDL Initiative toward ASIC Libraries.

The intent of VITAL was to provide a set of standard practices for modeling ASIC primitives, or macrocells, in VHDL and in the process make acceleration possible. Two VHDL packages were written: a primitives package and a timing package. The primitives package modeled all the gate-level primitives found in Verilog.

Because these primitives were now in a standard package known to the simulator writers, they could be optimized by the VHDL compilers for faster simulation. The timing package provided a standard, acceleratable set of procedures for checking timing constraints, such as setup and hold, as well as pin-to-pin propagation delays. The committee writing the VITAL packages had the wisdom to avoid reinventing the wheel. They chose the same SDF file format as Verilog for storing and annotating timing values.

SDF is the Standard Delay Format, IEEE Standard 1497. It is a textual file format for timing and delay information for digital electronic designs. It is used to convey timing and delay values into both VHDL and Verilog simulations. Another stated goal of VITAL is model maintainability. It restricts the writer to a subset of the VHDL language and demands consistent use of provided libraries. This encourages uniformity among models, making them easily readable by anyone familiar with VITAL. Readability and having the difficult code placed in a provided library greatly facilitate the maintenance of models by engineers who are not the original authors.

VITAL became IEEE Standard 1076.4 in 1995. It was reballoted in 2000. The 2000 revision offers several enhancements. These include support for multisource interconnect timing, fast path delay disable, and skew constraint timing checks. However, the most important new feature is the addition of a new package to support the modeling of static RAMs and ROMs.

Author: Keshav K, MindTree, Bangalore, India

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  1. Im not sure what verilog is but you seem to know quite alot about them.

  2. Who is the author of this article? It would be nice to credit them.

    Also, is VITAL still used? I know it was important when created, and I wonder if people still do gate-level VHDL simulation.

  3. Updated: Keshav K of MindTree Bangalore is the Orginal Author who emailed this article!

    We did understand from some of readers in the past that TI, Infineon, NXP etc still do some limited VHDL based GLS simulations.


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