Webinar Watch - Synopsys, A Structured Methodology for Verifying Low Power Designs

An in-depth technical webinar focusing on low power verification methodology.

On Tuesday, March 31, 2009 5:00 pm, Pacific Daylight Time (GMT -07:00, San Francisco)
Panelist(s) Info: Krishna Balachandran, Director of Low Power Verification Marketing, Srikanth Jadcherla, Group R&D Director, Janick Bergeron, Synopsys Fellow
Duration: 1 hour
Description: Power management and low power design bring a whole new assortment of bugs and failure mechanisms to IC designs. The task of verification, already a critical path in the delivery of the chip, now needs to take on additional tests and flows to ensure that the power management scheme is functional.

The complexity of power management and the broad spectrum of design scenarios could easily lead to escaped bugs without a rigorous methodology in place. In this webinar, we will focus first on the complexities and changes brought about in the low power era and the bugs types that are new to low power design. We will then cover the process of rigorous verification for low power and present a structured and reusable methodology for low power. The webinar will highlight the VMM extensions to base classes for low power that can be quickly used to replicate an efficient verification environment for low power designs. All the concepts covered in this webinar are detailed in the recently published "Verification Methodology Manual for Low Power" (VMM-LP), which customers of Synopsys can download in a PDF form from www.vmmcentral.org/vmmlp.

Register Now!

Following the presentation, a formal Q&A will take place.

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