Showing posts with label Seminars. Show all posts
Showing posts with label Seminars. Show all posts

Stoke Technical Seminar Series - Wireless

If you live in Bangalore, India this might be of interest to you.
Stoke Technical Seminar Series focus on 3G Mobile Data Offload, Emergence of LTE Technology, Integrated WiFi and Seamless Mobility, Stoke SSX Product Family Evolution.

A Must Attend For:

* Telecom Service Providers
* Cellular Service Providers - GSM & CDMA
* VAS Technology & Platform Companies
* Content Aggregators
* Content Owners
* Entertainment & Electronic Media
* Next Generation Mobile Content Solution Providers
* Telecom Associations & Regulators
* Handset Manufacturers - GSM & CDMA
* Portal Providers
* VAS Consulting and Research Organisations
* Venture Capitalists
* Multimedia Service Providers
* Software Developers
* System Integrators
* Mobile Internet Applications & Solution Developers
* DOT, DIT, Ministries & Regulatory

More details here..

INDIA Seminar Series 2010 - Modern Design Processes

An exciting agenda has been developed by Altium that will highlight many of the challenges facing today's electronics industry as well as put forward a case for rethinking tools and strategies to better align design capabilities with your current needs

Topics of focus will include:

* Design Process Management
* Design Team collaboration
* Collaborative PCB Design
* Design Data Management
* Version Control
* Also preview exciting new technology coming soon in the latest release of Altium Designer.

Who should attend:
Electronics Engineers, Electronics Managers, Team Leaders, Electronics Designers, Technical Directors, Technical Managers

For more info, please contact:
Rajesh Sawant +91 9663466910

Tech Talk - The Bleeding Edge (Oracle India, Sun Microsystems BU)

Last week i was invited to a Tech Talk organized by Oracle India (Sun Microsystems BU). The title of the talk was "Tech Talk - The Bleeding Edge, Evade your challenges– A dive into critical issues affecting High-end bleeding edge Semiconductors designs and the development engineers face off". The speaker was Mr. Sridhar Vajapey, VP, Hardware Development (Sun Microsystems BU), Oracle Corporation Inc.

The talk was highly informative covering the aspects of Semiconductor process Technology and challenges affecting the lower technology nodes of 28nm. The speaker also provided some very good insight into Sparc processor development, thermal management in a data center and issues with recreating silicon failures. Mr. Sridhar captivated the audience with his detail oriented talk and also dedicated time for answering questions from the audience. What kept me wondering was, how a VP kept himself up to date with technical details, issues and facts of current technologies. By the way did you ever wonder what Cutting edge, Leading Edge and Bleeding edge refer to? Do you know what they really mean?

MIPI & SoC Integration Lunch & Learn Seminar

Cadence Design Systems and Virage Logic would like to invite you to an interactive Lunch and Learn session that is designed to provide the latest information about MIPI standards, how to design-in an optimized MIPI solution, and how to develop an effective verification strategy for MIPI System-on-Chip (SoC) integration success!
Seating is limited - Register Now

Wednesday, April 21, 2010                    This is a Free Educational Event
Cadence Design Systems                      Registration: 10:00 am - 10:30 am
2655 Seely Avenue                                Seminar: 10:30 am - 1:00 pm
Building 10 Auditorium                            Lunch Will Be Served  
San Jose, CA  95134
(off Montague Expressway near 880)
Can't Make It?
Here's an Online Solution:
Cadence provides online self-guided Hands-On trials of Verification IP and tools for you to test drive at your desk - no downloads, no installation, and no licenses to manage.

Sponsored Post: SpyGlass 4.2.0 Webinar from ATRENTA

In this SpyGlass(R) webinar, Atrenta experts will take you through the highlights of the new release and cover the following topics, including overviews of:

* Latest GuideWare™ methodology improvements for better productivity
* New Atrenta Console™ interface for improved ease of use (demo included)
* CDC Setup Manager (demo included)
* Multi-mode timing coverage report, including why it's valuable
* New at-speed test analysis
* CPF and UPF support

Title:SpyGlass 4.2.0 Webinar
Date:Wednesday, May 6, 2009
Time:7:00 PM - 8:00 PM PDT

After registering you will receive a confirmation email containing information about joining the Webinar.
Space is limited.Reserve your Webinar seat now at:

Webinar watch: Accelerating Time-To-SI-Closure

Webinar:Accelerating Time-To-SI-Closure
Date:Tuesday, March 31, 2009
Time: 11 amPT / 2 pm ET
Duration: 60Minutes

Register now @:

Liveattendees who also submit the feedback form will be eligible to win a FREE 8GBiPod Touch (value approx. $250).

Accelerating Time-to-SI –Closure:
Unmanagedtiming-ECOs during the final stages of design can severely impact your tapeout schedule. Join our experts to learn how to usesignoff-driven SI-closure to keep your schedule on track and your performanceon target. This is the first in IC Compiler 2009 Webinar Series highlightingkey technologies for speeding design closure. Up-coming topics includeplacement-congestion minimization, power-rail design and in-design physicalverification.

Dr. Henry Sheng
Dr. Henry Sheng is R&D Group Director for Design Closure in ICCompiler. Henry and his organization are responsible for implementationextraction, timing and signal integrity, as well as Multi-corner Multi-mode(MCMM) and post-route closure. He has been with Synopsys since 1996. Henryholds a Ph.D. degree in Electrical Engineering and Computer Science from theUniversity of California, Berkeley.

Dr. Jinan Lou
Dr. JinanLou received his B.S. degree in Computer Engineering and Computer Science, M.S.and Ph.D. degrees in Computer Engineering, from University of SouthernCalifornia, Los Angeles, in 1993, 1995 and 1999, respectively. He is currentlya Principal Engineer at Synopsys. His research interests include physicaloptimization, layout driven logic synthesis and post-layout optimization fordeep-submicron technologies.

Webinar Watch - Synopsys, A Structured Methodology for Verifying Low Power Designs

An in-depth technical webinar focusing on low power verification methodology.

On Tuesday, March 31, 2009 5:00 pm, Pacific Daylight Time (GMT -07:00, San Francisco)
Panelist(s) Info: Krishna Balachandran, Director of Low Power Verification Marketing, Srikanth Jadcherla, Group R&D Director, Janick Bergeron, Synopsys Fellow
Duration: 1 hour
Description: Power management and low power design bring a whole new assortment of bugs and failure mechanisms to IC designs. The task of verification, already a critical path in the delivery of the chip, now needs to take on additional tests and flows to ensure that the power management scheme is functional.

The complexity of power management and the broad spectrum of design scenarios could easily lead to escaped bugs without a rigorous methodology in place. In this webinar, we will focus first on the complexities and changes brought about in the low power era and the bugs types that are new to low power design. We will then cover the process of rigorous verification for low power and present a structured and reusable methodology for low power. The webinar will highlight the VMM extensions to base classes for low power that can be quickly used to replicate an efficient verification environment for low power designs. All the concepts covered in this webinar are detailed in the recently published "Verification Methodology Manual for Low Power" (VMM-LP), which customers of Synopsys can download in a PDF form from

Register Now!

Following the presentation, a formal Q&A will take place.

The Future of High Performance Memory!

Rambus logo

Rambus India Design Seminars

The Future of High Performance Memory Designs

21 February 2008 | The Leela Palace Kempinski Bangalore | Bangalore, India

In this seminar, we will explore the types of memory systems required for next generation consumer applications and discuss how these advanced memory systems will solve tomorrow's system challenges. We will discuss innovative techniques developed by Rambus to improve memory performance and reduce overall system costs, as well as analyze solutions to multi-GHz memory designs. Finally, we will unveil the newest development from Rambus, the Terabyte Bandwidth Initiative, which enables 1 TB/s of memory bandwidth performance into a single SoC.

There is no cost for this seminar, but you must register to attend. Sign up early, as space is limited.

Who should attend?
Anyone who designs or manufactures digital consumer electronic systems or memory subsystems, including:
System Designers
System Manufacturing Engineers
Chip Architects
Technical Managers
Product Marketing

9:30 – 10:00
10:00 – 10:05
10:05 – 11:00
Evolution of Memory
11:00 – 12:15
XDR™/XDR2 and Memory Requirements for Next Generation Consumer Products
12:15 – 13:30
Lunch and Product Demonstrations
12:30 – 14:15
Solving System Engineering Challenges in High Speed Memory Designs
14:15 – 15:00
DDR2/DDR3 Bimodal Controller Design
15:00 – 15:15
15:15 – 16:00
Terabyte Bandwidth Initiative
Demonstrations and Q&A
Technical experts from Rambus will conduct demonstrations and answer questions at the end of the main session. Lunch will be provided to all attendees, and Rambus experts will be available during the lunch hour to answer questions.

This message was sent by Electronic Engineering Times eeMail broadcast service on behalf of Rambus.

For further assistance or more information about our full range of sourcing products and services, please contact us at Customer Services, 1 Sims Lane #08-01, Singapore 387355; phone: (65) 6547-2800; fax: (65) 6547-2888; e-mail: