Best known modelling practices for gigabit serial design - Live Webcast

This presentation will go over some of the common issues encountered when setting up performing circuit simulation of high speed serial designs. Topics will include s-parameter passivity and causality, frequency sampling and bandwidth and how they relate to simulation accuracy, model concatenation, and correlation between the time and frequency domains.

This webcast is Hosted by EDN and Sponsored by ANSYS.

Register Now - Click Here

Presenter:
Daniel Dvorscak,
Senior Application Engineer,ANSYS, Inc.

Date: March 25, 2011
Time: 3:00 PM ET / 12:00 PM PT

MIPI & SoC Integration Lunch & Learn Seminar

Cadence Design Systems and Virage Logic would like to invite you to an interactive Lunch and Learn session that is designed to provide the latest information about MIPI standards, how to design-in an optimized MIPI solution, and how to develop an effective verification strategy for MIPI System-on-Chip (SoC) integration success!
 
Seating is limited - Register Now

Wednesday, April 21, 2010                    This is a Free Educational Event
Cadence Design Systems                      Registration: 10:00 am - 10:30 am
2655 Seely Avenue                                Seminar: 10:30 am - 1:00 pm
Building 10 Auditorium                            Lunch Will Be Served  
San Jose, CA  95134
(off Montague Expressway near 880)
 
Can't Make It?
Here's an Online Solution:
 
Cadence provides online self-guided Hands-On trials of Verification IP and tools for you to test drive at your desk - no downloads, no installation, and no licenses to manage.

Sponsored Post: SpyGlass 4.2.0 Webinar from ATRENTA

In this SpyGlass(R) webinar, Atrenta experts will take you through the highlights of the new release and cover the following topics, including overviews of:

* Latest GuideWare™ methodology improvements for better productivity
* New Atrenta Console™ interface for improved ease of use (demo included)
* CDC Setup Manager (demo included)
* Multi-mode timing coverage report, including why it's valuable
* New at-speed test analysis
* CPF and UPF support


Title:SpyGlass 4.2.0 Webinar
Date:Wednesday, May 6, 2009
Time:7:00 PM - 8:00 PM PDT

After registering you will receive a confirmation email containing information about joining the Webinar.
Space is limited.Reserve your Webinar seat now at: https://www1.gotomeeting.com/register/439111672

Webinar watch: Accelerating Time-To-SI-Closure

Webinar:Accelerating Time-To-SI-Closure
Date:Tuesday, March 31, 2009
Time: 11 amPT / 2 pm ET
Duration: 60Minutes

Register now @:
http://TIG.cmptechnetwork.com/cgi-bin4/DM/y/eA0KLkvJ0A0HEhi0Ez

Liveattendees who also submit the feedback form will be eligible to win a FREE 8GBiPod Touch (value approx. $250).

Accelerating Time-to-SI –Closure:
Unmanagedtiming-ECOs during the final stages of design can severely impact your tapeout schedule. Join our experts to learn how to usesignoff-driven SI-closure to keep your schedule on track and your performanceon target. This is the first in IC Compiler 2009 Webinar Series highlightingkey technologies for speeding design closure. Up-coming topics includeplacement-congestion minimization, power-rail design and in-design physicalverification.

Presenters:
Dr. Henry Sheng
Dr. Henry Sheng is R&D Group Director for Design Closure in ICCompiler. Henry and his organization are responsible for implementationextraction, timing and signal integrity, as well as Multi-corner Multi-mode(MCMM) and post-route closure. He has been with Synopsys since 1996. Henryholds a Ph.D. degree in Electrical Engineering and Computer Science from theUniversity of California, Berkeley.

Dr. Jinan Lou
Dr. JinanLou received his B.S. degree in Computer Engineering and Computer Science, M.S.and Ph.D. degrees in Computer Engineering, from University of SouthernCalifornia, Los Angeles, in 1993, 1995 and 1999, respectively. He is currentlya Principal Engineer at Synopsys. His research interests include physicaloptimization, layout driven logic synthesis and post-layout optimization fordeep-submicron technologies.

Webinar Watch - Synopsys, A Structured Methodology for Verifying Low Power Designs

An in-depth technical webinar focusing on low power verification methodology.

On Tuesday, March 31, 2009 5:00 pm, Pacific Daylight Time (GMT -07:00, San Francisco)
Panelist(s) Info: Krishna Balachandran, Director of Low Power Verification Marketing, Srikanth Jadcherla, Group R&D Director, Janick Bergeron, Synopsys Fellow
Duration: 1 hour
Description: Power management and low power design bring a whole new assortment of bugs and failure mechanisms to IC designs. The task of verification, already a critical path in the delivery of the chip, now needs to take on additional tests and flows to ensure that the power management scheme is functional.

The complexity of power management and the broad spectrum of design scenarios could easily lead to escaped bugs without a rigorous methodology in place. In this webinar, we will focus first on the complexities and changes brought about in the low power era and the bugs types that are new to low power design. We will then cover the process of rigorous verification for low power and present a structured and reusable methodology for low power. The webinar will highlight the VMM extensions to base classes for low power that can be quickly used to replicate an efficient verification environment for low power designs. All the concepts covered in this webinar are detailed in the recently published "Verification Methodology Manual for Low Power" (VMM-LP), which customers of Synopsys can download in a PDF form from www.vmmcentral.org/vmmlp.

Register Now!

Following the presentation, a formal Q&A will take place.

CoWare upcoming webinars!

CoWare the leading global supplier of platform-driven electronic system-level (ESL) design software and services is arranging a series of online Webinars based on Processor Design, Software Development and Wireless Design to benefit the user. The webinars will be held on the following dates:

Wednesday, 18th March:
Custom Processor / Programmable Accelerator Design and Implementation.

Tuesday, 31st March:
Getting Started with Virtual Platforms: A Software Developer Perspective.

Wednesday, 8th April:
Challenges for LTE Wireless Systems Design.

These webinars will also be recorded for viewing it later as per participant’s convenience.

Here are the details of the Webinars with the registration link:
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Wednesday, March 18, 2009
9 am Pacific (9:30 PM IST)
Length: 1 hour
Presenter: Drew Taussig

Custom Processor / Programmable Accelerator Design and Implementation
As companies are looking to improve their competitive advantage, the need for programmable hardware accelerators, ASIPs and custom processors is growing rapidly. They provide the solution to performance and flexibility challenges electronic system designers are facing today. But, in today s economy where there are fewer resources and everyone has cost reduction on their mind, how can you design them efficiently? How can you generate efficient RTL? How can you equip the software developers with the right linker, assembler, compiler, simulator and debugger?

What you will learn:
* Concepts and reasons behind developing custom processors and hardware programmable accelerators.
* Design and implementation steps and how these steps can be streamlined using efficient and powerful design tools that automate the exploration, RTL implementation and software development tools.
* How the generated processor can be used for development and verification in a Virtual Platform for Software Development, an FPGA or an RTL emulation environment.

Register now!

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Tuesday, March 31, 2009
9 am Pacific (9:30 PM IST)
Length: 1 hour
Presenter: Achim Nohl

Getting Started with Virtual Platforms: A Software Developer Perspective
The ability to debug and analyze software defects efficiently is a key requirement in order to complete a software project successfully and on time. Especially when porting legacy software such as an OS or migrating sequential code to multi-core platforms, powerful debugging tools and methods are indispensable. This one hour webinar gives a technical overview and various practical examples on the usage of virtual platforms for debugging. Virtual platforms enable a whole new world of software analysis and debugging solutions. An OS-aware software analysis framework eases the understanding of the history and interaction between multiple parallel software stacks. The controllability and visibility of virtual platforms enables engineers to trigger and analyze multi-processing defects such as dead-locks and race conditions. Correctness and performance of complex shared-memory communication, task scheduling and control can be asserted which results in a significant quality and productivity gain for the software engineer.

What you will learn:
* Overview of the debugging infrastructure provided by a virtual platform
* Practical examples for applying virtual platforms for embedded software debugging based on real world software and hardware configurations
* How the OS-aware analysis and debug framework can be used and customized to debug typical problems that appear during OS porting
* How domain integration problems in an asymmetric, multi-processing platform can be identified
* How virtual platforms can be used to debug shared memory communication problems based on a multi-core video driver
* How virtual platforms can be used to spot an existing bug in the Linux kernel for the ARM11 MPcore configuration

Register now!

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Wednesday, April 8, 2009
9 am Pacific (9:30 PM IST)
Length: 1 hour
Presenter: Dr. Johannes Stahl

Challenges for LTE Wireless Systems Design
Long-Term Evolution (LTE) wireless systems have 5-10x higher processing complexity than currently-deployed 3G wireless systems. This creates a unique pressure across all aspects of the handsets, the basestation and the network. Previous product platforms have to be significantly re-architected and entirely new software applications have to be developed to take advantage of the much higher bandwidth that LTE is targeted to provide. In this webinar, we will explain those design challenges and offer different approaches that design teams can take to deliver advanced products. The webinar targets development managers across the supply chain that are developing LTE products today or are planning to get involved in the near future. Whether you are a manager inside a network operator, basestation or handset OEM or you are in a semiconductor company, you should participate and learn about how you can meet your LTE product roll-out schedule within your tight development budgets.

What you will learn:
* How network operators can leverage the LTE standard to optimize their network throughput
* How chip architects will extract maximum application performance from their architectures
* How programmability of signal processing accelerators does not come at the expense of too much power
* How application or baseband processing software is developed if it is spread across multiple processor cores

Register now!