Latch
Are latches really bad for a design?
It is not completely correct to say that we have to avoid latches in our designs. In one of our recent projects we went…
Coding Guidelines
VHDL Coding Guidelines
HDL Coding Guidelines - Part 7
Hints Avoid more package references than needed Keep all objects and subprograms in the nearest possible scope Keep loc…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 6
To Avoid common Warnings Store each VHDL unit into a separate file except package header and body Signal assignments fo…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 5
Critical Policies to Keep note! Balance clock to delta accuracy Pull-ups and pull-downs have to be modeled on chip leve…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 4
To Avoid common Errors A configuration declaration is needed for each architecture in the design Design-internal refere…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 3
Portability Language for modeling should be VHDL-87 VHDL-93 keywords should not be used Verilog keywords should not be…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 2
When Compiling (VHDL): A configuration declaration is needed for each architecture in the design Design-internal refere…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 1
Coding of circuit behavior and architecture is one of the most critical steps in the whole chip development project. It…
Learning
Delay Modelling and Coding Guidelines
In digital logic design, there are different types of delay modeling. Some of the commonly used delay modeling techniqu…