Transistor sizing / multi-Vt design

This task usually starts with a placed and routed design, then generating a transistor level netlist for it and further optimizing it. Optimization can be for example adjusting transistor widths, or assigning different transistor threshold voltages in a dual threshold voltage design. This can be done algorithmically (e.g. TILOS) or in an ad-hoc fashion. See how much timing improvement you get vs. just gate-level optimization. Also notice any "error" in STA methodology and highlight it further.  Following timing optimization, further optimize the design to reduce power  consumption without losing any timing.

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