Physical Design
Clock network design
In this blog post, we will discuss some of the challenges and techniques involved in designing a clock network for a ve…
Physical Design
Physical Design
IR drop driven placement
The objective here is to explore placement techniques which can lead to reduction in IR drop. One way to do this is to …
Physical Design
Impact of dummy fill on timing
How can you quantify the impact of dummy fill on post-layout timing? Dummy fill can be inserted into a layout using SO…
Timing
The effect of whitespace and aspect ratio on wirelength and timing
Whitespaces (empty space) are inserted in layouts in order to increase the routing resources of the chip. Have you ever…
Statistical Timing Analysis
Investigation on timing analysis inaccuracies
Timing analysis inaccuracies due to crosstalk, multiple gate input switching, supply voltage variation, temperature, ma…
Physical Design
Distributions in statistical timing
How do you observe and highlight the impact of assumptions on gate-length variability distributions (if any) on final d…
Wire Length Models
Effect of WLM and target frequency on performance
How do you quantify the effect of WireLength Models (WLM) and target frequency on the post-routing timing results?
Physical Design
Clock driver input alignment
Modern clock networks include several drivers in which delays are affected by the timing of their input signal transiti…
Re-Timing
Re-timing tackles long combinational logic paths
Re-timing reduces longest combinational logic paths by relocating some of the flip-flops, both logically and physically…
Technology Mapping
Transistor level technology remapping
This is a process of combining several cells to form new library cells, and to optimize a transistor level netlist. Thi…
Sizing
Transistor sizing / multi-Vt design
This task usually starts with a placed and routed design, then generating a transistor level netlist for it and further…
TechOnline
Restrictive Design Rules and Their Impact on 22nm Design and Physical Verification
Process variability is posing considerable challenge to the capability of lithography and manufacturing techniques, an…