Showing posts with the label Physical Design

Clock network design

IR drop driven placement

Impact of dummy fill on timing

The effect of whitespace and aspect ratio on wirelength and timing

Investigation on timing analysis inaccuracies

Distributions in statistical timing

Effect of WLM and target frequency on performance

Randomized algorithm/approximation scheme for statistical timing analysis

Clock driver input alignment

Re-timing tackles long combinational logic paths

Transistor level technology remapping

Transistor sizing / multi-Vt design

Backend physical design Interview Questions

Restrictive Design Rules and Their Impact on 22nm Design and Physical Verification

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