The Digital Electronics Blog

Clock Networks

Clock network design

mg -3:58 PM BBC 1

IR drop

IR drop driven placement

mg -3:21 PM BBC 1

Interview Questions

Impact of dummy fill on timing

mg -9:58 PM BBC 1

Interview Questions

The effect of whitespace and aspect ratio on wirelength and timing

mg -7:00 PM BBC 1

Crosstalk

Investigation on timing analysis inaccuracies

mg -5:41 PM BBC 1

Interview Questions

Distributions in statistical timing

mg -5:41 PM BBC 1

Interview Questions

Effect of WLM and target frequency on performance

mg -4:12 PM BBC 1

Interview Questions

Randomized algorithm/approximation scheme for statistical timing analysis

mg -4:09 PM BBC 1

Clock Networks

Clock driver input alignment

mg -4:09 PM BBC 1

Clock Skew

Re-timing tackles long combinational logic paths

mg -4:08 PM BBC 1

Physical Design

Transistor level technology remapping

mg -3:36 PM BBC 1

Multi-Vt

Transistor sizing / multi-Vt design

mg -3:35 PM BBC 1

Backend

Backend physical design Interview Questions

Murugavel -1:38 PM BBC 1

22nm

Restrictive Design Rules and Their Impact on 22nm Design and Physical Verification

mg -2:35 PM BBC 1