VLSI/ASIC/VHDL Interview Questions

One of the most popular topics on this blog is the series on Interview Questions. With over 105 Interview Questions, many of which are original and unique we continue in that trend to post a new set today. It just does not stop here. The person who can answer all questions right in the comments sections, stands a chance to win a Home Burglar Alarm device with integrated motion sensor** (Details will be posted later and the product will only shipped to addressee in India).

Now for the Questions!
1. For a combinational process in VHDL, the sensitivity list should contain all of the signals that are read in the process. Please give a detailed reason and an exception to this statement.
2. For a combinational process, every signal that is assigned to, must be assigned to in every branch of If-Then-Else statement and Case statement. Why?
3. Each signal should be assigned to in only one process. Please give a detailed reason and an exception to this statement.
4. Separate unrelated signals into different processes. Give atleast two reasons!
5. In a state-machine, illegal and unreachable states should transition to the reset state. Explain.
6. If your state-machine has less than 16 states, use a one-hot encoding. Explain.
7. Include a reset signal in all clocked circuits. Explain.
8. For implicit state-machines, check for reset after every wait statement.
9. Connect reset to the important control signals in the design, such as the state signal. Do-not reset every flip-flop. Explain.
10.Use synchronous, not asynchronous reset. Explain.

**Only original answers will be eligible for the lucky draw. Google searched and copied answers will be disqualified.
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Good luck.

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  1. 1> If this is not done, then even if the output is assigned the value of the input signal which has not transitioned, i.e. unintentional assignment of input to output

    3> This will lead to multiple driver problems. ex If a signal is being driven in two always blocks being clocked by same/different clocks.


    7> If not reset, then signals will be undefined from the period reset is low to the period clock starts


    10> If reset is synchronous, then the output signal is undefined until clock is present, undefined from reset =0 to clock pulse.

  2. Can you answer the rest of the questions?


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