The stuck-at fault (SAF) model assumes that a single signal line in the circuit is permanently fixed at logic 0 or logic 1, and it is tested with one pattern applied at any speed. The transition-delay fault (TDF) model assumes that a line is too slow to rise or too slow to fall, and it is tested with a pair of patterns: the first sets the line to its starting value, the second launches the transition, and the result is captured one functional clock period later. Production test uses both: SAF screens static defects such as shorts and hard opens, while TDF screens timing-related defects that only show up at speed.
Key takeaways
- A stuck-at fault sits on a net or gate pin, not on a whole gate. Every line has two faults: stuck-at-0 (s-a-0) and stuck-at-1 (s-a-1).
- A transition-delay fault also comes in two forms per line: slow-to-rise (STR) and slow-to-fall (STF).
- SAF needs one vector and can be applied with a slow scan clock. TDF needs two vectors and an at-speed launch and capture, usually from on-chip clocks.
- TDF patterns also detect most stuck-at faults on the same lines, but not all, so SAF and TDF pattern sets are normally run together.
- Neither model targets bridging faults directly. Those need their own models (bridging, cell-aware) or are caught as a side effect.
Where fault models fit in design for test
In the context of silicon design for test (DFT), there are several techniques and methodologies that are used to improve the testability of integrated circuits (ICs) during the manufacturing process. Some of the commonly used DFT techniques in silicon design are:
- Built-in self-test (BIST): test circuitry embedded in the IC generates patterns and checks the responses on chip. Memory BIST and logic BIST are the common forms.
- Boundary scan: extra cells at the device pins, defined by IEEE 1149.1, allow the interconnects on the board and the components connected to them to be tested.
- Scan chain: the flip-flops of the design are replaced by scan flip-flops and connected in serial chains, so the internal logic can be loaded and observed directly.
- Test compression: on-chip decompressors and compactors reduce the volume of test data that must be stored on the tester and shifted in, which cuts test time.
- At-speed testing: the IC is tested at the clock rate it will run in the final product, which finds timing-related defects that a slow test misses.
These techniques are used to make sure that ICs leave the factory with high quality and reliability, and that defective parts are caught before they are shipped to customers.
A fault model is the bridge between real physical defects and the patterns that an automatic test pattern generation (ATPG) tool creates. Defects are messy: a missing via, a resistive contact, a particle that shorts two wires, a weak transistor. ATPG cannot reason about every possible defect, so it works on a simple logical abstraction of them. The stuck-at and transition-delay models are the two abstractions that almost every digital production test flow is built on.
The stuck-at fault model
A stuck-at fault (SAF) model is a type of fault model used in digital circuit testing and Design for Testability (DFT) techniques.
In this model, it is assumed that a single signal line in the circuit, a gate input, a gate output or a net, is permanently stuck at logical 0 or 1, regardless of the values applied to the circuit. Physically this can be caused by a variety of defects, such as a short to power or ground, a broken wire, or a faulty transistor. Stuck-at faults are the simplest and most widely used fault model in digital circuits, and patterns that detect them also catch many other defects as a side effect. The usual assumption is the single stuck-at fault: only one line is faulty at a time. That keeps the fault list manageable (two faults per line) and, in practice, a test set with high single-fault coverage also detects most multiple-fault cases.
How a stuck-at fault is detected
To detect a stuck-at fault, a pattern has to do two things:
- Activate (excite) the fault: drive the faulty line to the opposite of its stuck value. To test s-a-0, the line must be set to 1 in the good circuit.
- Propagate the fault effect: set the other inputs along a path so that the difference between the good and faulty value reaches an observable point, a primary output or a scan flip-flop.
Take a two-input AND gate with inputs A and B and output Y. To test A s-a-0, set A = 1 so the fault is activated, and set B = 1, the non-controlling value of AND, so A reaches Y. The good circuit gives Y = 1 and the faulty circuit gives Y = 0. The pattern A=1, B=1 is a test for A s-a-0.
Worked example: fault list and fault collapsing
The same AND gate has three lines (A, B, Y), so six stuck-at faults. Several of them cannot be told apart from the outputs:
| Fault | Test pattern (A, B) | Good Y | Faulty Y | Note |
|---|---|---|---|---|
| A s-a-0 | 1, 1 | 1 | 0 | Equivalent to B s-a-0 and Y s-a-0 |
| B s-a-0 | 1, 1 | 1 | 0 | Same test as above |
| Y s-a-0 | 1, 1 | 1 | 0 | Same test as above |
| A s-a-1 | 0, 1 | 0 | 1 | Needs its own test |
| B s-a-1 | 1, 0 | 0 | 1 | Needs its own test |
| Y s-a-1 | 0, 1 or 1, 0 | 0 | 1 | Detected by either test above |
A s-a-0, B s-a-0 and Y s-a-0 produce exactly the same faulty behaviour, so they are equivalent and can be collapsed into one. The six faults become four classes, and three patterns (11, 01, 10) detect all of them. ATPG tools do the same collapsing on millions of lines, which is why reports often quote both a full and a collapsed fault count.
Coverage and untestable faults
Not every fault can be detected. Some are redundant (the logic masks them under all inputs), some are blocked by tied or constrained signals, and some sit in logic the scan structure cannot reach. ATPG reports therefore separate fault coverage (detected faults over all faults) from test coverage (detected faults over faults that can be tested). The exact definitions vary a little between tools, so always check which one a report is quoting before comparing numbers between projects.
The transition-delay fault model
The Transition Delay Fault (TDF) model is another fault model used in digital circuit testing and Design for Testability (DFT) techniques.
In this model, faults are modelled as delays in the propagation of signals through the circuit. Specifically, a TDF assumes that a transition at one line, either rising or falling, is delayed so much that it does not reach any capture point within one clock period, whatever path it takes. This can be caused by various defects such as a weak transistor, a resistive via or contact, or a partially broken wire. The model keeps the simplicity of stuck-at: one location, two fault types per line (slow-to-rise and slow-to-fall), and it is easy for ATPG to target.
How a transition fault is detected
A transition fault needs a two-pattern test:
- Initialisation vector (V1): sets the target line to its starting value, 0 for a slow-to-rise test.
- Launch vector (V2): changes the line to the final value, 1 for slow-to-rise, and also sensitises a path to a capture flip-flop. V2 on its own is effectively a stuck-at test for the opposite value: slow-to-rise on a line is detected like a temporary s-a-0.
- Capture: the capture flip-flop is clocked one functional period after the launch. If the transition is late, the old value is captured and the fault is detected.
In a scan design the two vectors are created in one of two ways:
| Method | How V2 is created | Strengths | Weaknesses |
|---|---|---|---|
| Launch-on-capture (LOC), also called broadside | V1 is shifted in; V2 is the circuit's own response to V1 after one functional clock | Scan enable can be slow; only functional paths are exercised | Harder for ATPG, usually lower coverage and more patterns |
| Launch-on-shift (LOS), also called skewed-load | V2 is V1 shifted by one more bit in the scan chain | Easier for ATPG, often higher coverage | Scan enable must switch at speed; may exercise non-functional paths and over-test |
A common misunderstanding is that the tester measures delay during a TDF test. In modern practice it does not. It shifts the patterns in slowly, and an on-chip clock controller (driven by the device PLL) issues the fast launch and capture pulses. The test is pass or fail for a given capture period. This is why at-speed test is less dependent on expensive high-speed tester channels than it once was.
Worked example: what TDF can and cannot catch
Illustrative numbers. Suppose the clock period is 1.00 ns and a path through a target line has a nominal delay of 0.60 ns, giving 0.40 ns of slack. The TDF test launches through this path and captures at 1.00 ns.
- A resistive via adds 0.55 ns. The path now takes 1.15 ns, the old value is captured and the part fails. Detected.
- A smaller defect adds 0.25 ns. The path takes 0.85 ns, the correct value is captured and the part passes. Missed, even though a longer path through the same line, with only 0.10 ns of slack, would have failed in the field.
The second case is the main limitation of TDF. ATPG is free to pick the easiest, often shortest, path, so small delay defects can escape. Timing-aware ATPG, which uses timing data to push tests along longer paths, and path-delay tests on critical paths are the usual answers.
SAF and TDF compared
| Aspect | Stuck-at fault (SAF) | Transition-delay fault (TDF) |
|---|---|---|
| What it assumes | A line is fixed at 0 or 1 | A line is too slow to rise or to fall |
| Faults per line | 2 (s-a-0, s-a-1) | 2 (slow-to-rise, slow-to-fall) |
| Patterns per test | One vector | Two vectors (initialise, launch) |
| Clocking | Slow capture is fine | Launch and capture at functional speed |
| Typical defects found | Hard shorts and opens, stuck transistors | Resistive opens and vias, weak drivers, gross delay defects |
| Coverage and pattern count | Easier to reach high coverage with fewer patterns | Usually lower coverage and noticeably more patterns |
| Main limitation | Blind to timing defects | Can miss small delay defects on short paths; at-speed power and IR drop must be managed |
Choosing between SAF and TDF, or using both
The choice of emphasis depends on the characteristics of the circuit and the test requirements. In most modern digital devices the answer is both: stuck-at patterns for static defects and transition patterns for timing defects. Here are the factors that change the balance:
- Circuit speed: if the circuit runs at high clock frequencies, or on an advanced process node where resistive defects are common, TDF patterns are needed because a slow test will pass parts that fail at speed.
- Defect types: SAF patterns cover static defects well. Delay defects need TDF or path-delay patterns. Bridging defects are not modelled by either and need bridging or cell-aware fault models, although SAF and TDF patterns catch many of them by chance.
- Test coverage: TDF targets a different class of defects, not a superset. A TDF pattern set will detect most stuck-at faults on the same lines, but some remain undetected, so a top-up set of stuck-at patterns is usually generated after TDF.
- Test equipment and test time: TDF needs an at-speed launch and capture. With on-chip clock control the tester only shifts data, but the larger pattern count still costs test time and tester memory, which compression helps to contain.
- Design complexity and quality targets: a small, slow design with a modest quality target may ship on stuck-at patterns alone. Automotive and data centre parts, with defect targets in the low parts per million, normally add TDF and often cell-aware and small-delay patterns as well.
Overall, the TDF model is an important tool for the reliability and quality of digital circuits, particularly where high-speed operation is critical. It does not replace the stuck-at model; it adds to it.
Common mistakes
- Saying a whole gate is stuck. Faults are placed on pins and nets. A two-input gate has three fault sites (two inputs, one output) and six stuck-at faults.
- Treating TDF coverage as a superset of SAF coverage. It is not. Run stuck-at top-up patterns.
- Comparing coverage numbers without checking the definition. Fault coverage and test coverage can differ by several points on the same design.
- Ignoring at-speed power. Many flops toggling in the launch cycle cause IR drop, which can slow paths and fail good parts. Low-power fill and pattern power limits help.
- Using launch-on-shift without checking scan enable timing. LOS needs a scan enable that can switch within one functional cycle, which is a timing closure task in its own right.
FAQ
Can one pattern set detect both stuck-at and transition faults?
Partly. The launch vector of a transition test also acts as a stuck-at test, so TDF patterns detect many stuck-at faults. The remaining stuck-at faults are targeted with a smaller top-up set.
Why is TDF coverage usually lower than SAF coverage?
Each TDF test needs two consistent vectors and a sensitised path in the launch state, which constrains ATPG far more than a single vector. With launch-on-capture the second vector is also fixed by the design's own logic.
What is the difference between a transition fault and a path-delay fault?
A transition fault sits on one line and is large enough to fail along any path through it. A path-delay fault is the total delay along one specific path from launch to capture. Path-delay tests are more precise but the number of paths grows very quickly, so they are used only on selected critical paths.
Do I still need functional test if I have high SAF and TDF coverage?
Usually some functional or system-level test remains, for analogue blocks, I/O, memories without BIST and defects that structural models miss. Structural scan test does most of the work for digital logic because it is fast, measurable and diagnosable.
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