India is often cited as having about 20% of the world's semiconductor design engineers. Until recently, almost none of them were designing chips for Indian companies. That is now changing, and fast.
India's semiconductor moment is the shift from supplying design engineers to the world's chip companies to building Indian-owned chip products and the factories to make them. Government programmes (the India Semiconductor Mission and its Design Linked Incentive scheme) have funded early tape-outs, a first wave of fabless startups has reached silicon and venture funding, and the first assembly plants and a 28nm fab are coming online. The next 18 months decide whether that turns into revenue and yield, or stays a story.
Key takeaways
- India has the design talent but has captured little of the IP value; policy since 2021 targets that gap directly.
- The DLI scheme has sanctioned 24 chip design projects across 23 startups and supported 16 startup tape-outs, as reported in early 2026.
- Reported startup funding in the sector grew from about $5 million in 2023 to about $50 million in 2025.
- Micron's Sanand ATMP began commercial production in February 2026; the Tata-PSMC 28nm fab at Dholera targets first wafers in December 2026.
- The open gaps are analog and mixed-signal IP, fab yield know-how, business and go-to-market talent, and ecosystem depth.
A note on the numbers
Indian figures are usually reported in crore: 1 crore is 10 million, so ₹100 crore is ₹1 billion. Dollar conversions below are as originally reported and depend on the exchange rate used at the time (roughly ₹83 to ₹88 per US dollar over 2023 to 2026), so small differences between sources are normal. Figures attributed to 2025 and 2026 are as published by the named sources and have not all been independently re-verified.
1. The sleeping giant awakens
For three decades India has been a global back office for semiconductor design: a country that supplies the engineers who design the world's chips but captures almost none of the value. The chips in your smartphone, your car and your home router were very likely designed, at least in part, by an Indian engineer. The company that made them? Almost certainly not Indian.
That structural anomaly (enormous talent, negligible IP ownership) is the foundational problem India's semiconductor policy is now trying to solve. After years of fits and starts, the evidence of 2025 and early 2026 suggests the ecosystem is finally building genuine momentum.
The Indian semiconductor market was valued at approximately $38 billion in 2023 and is estimated at $45 to 50 billion in 2025. Industry analysts project that it will cross $100 billion by 2030. More importantly, a generation of Indian-founded, India-headquartered fabless chip companies is moving from concept to silicon, and attracting serious institutional capital for the first time.
Reported startup funding in India's semiconductor sector grew tenfold in two years, from $5 million in 2023 to $50 million in 2025. The question is no longer whether India can design chips. It is whether it can build businesses around them.
2. The policy engine: ISM, DLI and what actually changed
India's semiconductor push is anchored in the ₹76,000 crore (about $8.67 billion at recent rates) Semicon India Programme, approved in December 2021, with the India Semiconductor Mission (ISM) as its nodal agency. Within it, the Design Linked Incentive (DLI) scheme is the instrument most directly aimed at startups.
What DLI actually does
The DLI scheme offsets the cost disadvantages Indian chip design companies face when competing globally. It works through two main mechanisms:
- Product Design Linked Incentive: performance-linked incentives of 4 to 6% of net sales turnover for five years, capped at ₹30 crore per applicant.
- Design Infrastructure Support: subsidised or free access to industry-grade EDA tools, multi-project wafer (MPW) fabrication slots and IP cores.
As of early 2026, the reported results are tangible:
- 24 chip design projects sanctioned across 23 startups
- ₹8.03 billion (₹803 crore, about $91.6 million) in total DLI project outlay committed, including EDA tool costs
- ₹234 crore in direct government support committed across 22 design projects
- ₹380 crore or more (about $43.9 million) raised from private VC investors by DLI-supported startups
- 72 or more companies granted access to advanced EDA tools, with over 2.25 crore (22.5 million) tool-hours recorded
- 67,000 students and over 1,000 startup engineers actively using the national chip design platform
- 16 startup tape-outs completed, and 6 chips fabricated at advanced foundry nodes, including 12nm
Worked example: what a DLI incentive is worth
An illustrative case, using the scheme's published structure rather than any real company: a startup reaching ₹100 crore of annual net sales in its first year of eligibility at 6% would earn ₹6 crore that year. With sales growing and the rate tapering towards 4% over five years, the total would approach the ₹30 crore cap only for a company selling well over ₹100 crore a year. For most early startups the infrastructure support (EDA licences and MPW shuttles worth crores before first revenue) is the more valuable half of the scheme.
ISM 2.0: deepening the bet
The Union Budget 2026 to 2027 marked a step change. The announcement of India Semiconductor Mission 2.0 signals a shift from ecosystem creation to ecosystem consolidation. The reported 2026 to 2027 outlay is ₹8,000 crore for the modified semiconductor and display programme, targeting at least one new fab, nine compound semiconductor or ATMP units, and expanding DLI coverage to approximately 30 design companies.
Critically, ISM 2.0 adds a dedicated ₹1,000 crore allocation for semiconductor equipment, materials and full-stack Indian IP, acknowledging that design leadership alone is not enough and that India needs indigenous tooling and materials over the medium term.
3. The startups: from tape-out to revenue
Below is a representative, not exhaustive, picture of the companies building India's chip design future. They differ in domain, stage and structure, but share a common origin story: deep technical founders, often from IISc or an IIT, attacking a specific market gap with indigenous IP.
| Company | Domain | Stage / funding (as reported) | Differentiator |
|---|---|---|---|
| Netrasemi | Edge AI / vision SoC | Series A: $14.6M total (Zoho-led) | AI camera SoC on TSMC 12nm; targeting surveillance, IoT |
| Mindgrove Technologies | SoC / MCU | Series A: ₹85 Cr ($8M) | Described as India's first commercial RISC-V MCU; IIT Madras incubated |
| FermionIC Design | SerDes / RF / mmWave | Seed/Series A: ₹50 Cr ($6M) | High-speed wireline and mmWave ICs for satellite, radar, 5G |
| AGNIT Semiconductors | GaN / RF / power | Seed: $3.5M round, $4.87M total at the time (3one4 / Zephyr Peacock) | IISc spinoff; GaN wafers and subsystems for defence, 5G |
| Morphing Machines | CGRA / AI processor | Seed: ₹23 Cr ($2.76M) | REDEFINE many-core reconfigurable processor for AI workloads |
| InCore Semiconductor | RISC-V processor IP | Seed: $3M (Peak XV) | SHAKTI spinoff; commercial RISC-V cores for SoC licensing |
| Saankhya Labs | 5G / SDR | Growth (part of Tejas Networks) | Software-defined radio for 5G, satellite, broadcast |
| C2i Semiconductors | Power / AI infrastructure | Pre-revenue: $4M | Server power management and AI infrastructure chips |
| Calligo Technologies | RISC-V / HPC | DLI-backed | Posit-based RISC-V co-processor (TUNGA) for HPC/AI |
| BigEndian Semiconductors | Vision SoC | Seed: $3M | Surveillance and embedded vision SoC; DLI cohort |
| Vervesemi Microelectronics | Motor control / ASIC | DLI-backed; ISRO tie-up | BLDC motor control ASICs for EV, drones, defence |
| Silizium Circuits | RF / analog IP | NXP FabCI cohort | Indigenous analog RF IP for 5G, GNSS and IoT |
Three patterns stand out. Most companies target a niche (vision, motor control, GaN RF, RISC-V IP) rather than general-purpose processors. Several are university spinoffs carrying a decade or more of lab R&D. And the rounds are small by global standards: a $3 million seed round would barely fund one advanced-node mask set, which is why DLI's MPW and EDA support matters so much.
Company spotlights
Netrasemi: Kerala's breakout story
Founded in 2020 in Thiruvananthapuram by Jyothis Indirabhai, Sreejith Varma and Deepa Geetha, Netrasemi has become the poster child of India's DLI success. Its July 2025 Series A of ₹107 crore, led by Zoho Corporation and Unicorn India Ventures, brought total funding to $14.6 million and established Kerala as a credible chip design location. The company's SoC targets edge AI for smart cameras and IoT on TSMC's 12nm node. Plans to double headcount from 83 to 166 engineers and complete mask production for three SoC families within 18 months make it one of the most execution-focused companies in the cohort.
AGNIT Semiconductors: India's GaN frontier
If Netrasemi represents the consumer edge of India's chip ecosystem, AGNIT represents its strategic depth. Founded in 2019 as a spinoff from the Indian Institute of Science (IISc) by seven researchers, AGNIT develops GaN wafers, devices and RF subsystems for defence, telecom (5G base stations, AESA radar, electronic warfare) and power electronics (EV chargers). Backed by over 15 years of IISc R&D, the company holds patent-protected technology across GaN materials, manufacturing processes and device design. Its October 2024 seed round of $3.5 million, co-led by 3one4 Capital and Zephyr Peacock, marked a notable milestone: a generalist VC firm making its first semiconductor bet, a sign of the sector's broadening appeal to institutional investors. A further seed extension of about $2.6 million, led by Shastra VC, was reported in March 2026.
InCore Semiconductor: the RISC-V IP play
Founded in 2018 out of IIT Madras's SHAKTI open-source processor initiative, InCore is building India's answer to Arm and SiFive. Its Azurite and Calcite RISC-V cores are designed for licensing into commercial SoC flows, competing directly with established processor IP vendors. The $3 million round from Peak XV Partners in May 2023 provided early validation, and the company has been progressing towards revenue-stage engagements with global customers. InCore is a pure IP play: it designs no chips of its own, instead building the foundational blocks that others integrate.
4. The hardware layer: fabs, ATMP and the Tata bet
Fabless chip design is India's immediate strength. But the country is also making a calculated bet on physical manufacturing: not to compete with TSMC at the leading edge, but to establish sovereign capacity and attract supply-chain diversification investment from global players.
Key infrastructure milestones (2025 to 2026)
- Micron ATMP, Sanand, Gujarat: India's first global semiconductor assembly and test facility, a ₹22,516 crore project, inaugurated by Prime Minister Modi on 28 February 2026 with the start of commercial production of memory modules. A major milestone in the ISM story.
- CG Semi OSAT pilot, Sanand: India's first end-to-end OSAT pilot line, launched in August 2025. CG Power's G1 facility handles about 0.5 million units per day; G2 is planned to scale to 14.5 million units per day.
- Tata-PSMC fab, Dholera: India's first commercial semiconductor fab, at 28nm and older nodes, targeting first wafer output in December 2026. This is the highest-stakes single milestone in India's semiconductor journey.
- HCL-Foxconn JV: groundbreaking ceremony reported on 21 February 2026, signalling serious intent from two major technology companies to establish joint semiconductor manufacturing in India.
- Silectric Semiconductor (Zoho-backed): a planned ₹3,425 crore SiC fab and ATMP near Mysuru, targeting domestic supply of EV power semiconductors.
- SCL Mohali modernisation: the government's own Semiconductor Laboratory is receiving ₹4,500 crore for modernisation and has been confirmed as not to be privatised.
The Tata-PSMC 28nm fab in Dholera is the most important single milestone in India's semiconductor ambitions. Success means not just first silicon; it means reaching competitive yields within 6 to 12 months of production. That is where the real test lies.
Why yield is the real test
An illustrative calculation shows why. Suppose a 300 mm wafer yields 600 candidate dies of a mid-sized 28nm chip and costs a fixed amount to process. At 50% yield the fab sells 300 good dies; at 90% it sells 540. The wafer cost is the same in both cases, so the cost per good die is 1.8 times higher at 50% yield. Mature 28nm lines elsewhere have run for over a decade; a new fab has to close that gap quickly or sell at a loss.
5. The geographic picture: India's chip design hubs
| Hub | Tier | Strength | Notable entities |
|---|---|---|---|
| Bengaluru | Primary (497 startups) | Full-stack design; IISc ecosystem; MNC R&D centres | AGNIT, FermionIC, Morphing Machines, Saankhya, C2i; Intel, AMD, Samsung, TI, Qualcomm R&D |
| Hyderabad | Primary | Telecom and SoC design; T-Hub hardware incubation | Silizium Circuits, MosChip, Ineda; Qualcomm's largest India R&D centre |
| Chennai / IIT Madras | Primary + academic | RISC-V leadership; SHAKTI ecosystem; OSAT (SPEL) | Mindgrove, InCore, BigEndian; IIT Madras SHAKTI programme |
| Pune | Secondary | Automotive and motor control; engineering services | Vervesemi; NXP, Marvell R&D |
| Noida / NCR | Secondary | Telecom chips; DRDO compound semiconductors | MBit Wireless; DRDO SSPL, Arm, NXP design centres |
| Dholera / Sanand, Gujarat | Fab zone | First commercial fab and ATMP infrastructure | Tata-PSMC fab, Micron ATMP, CG Semi OSAT, HCL-Foxconn JV |
| Thiruvananthapuram | Emerging hub | Edge AI; Zoho ecosystem investment | Netrasemi |
| Mysuru | Emerging fab | SiC / compound semiconductors (planned) | Silectric Semiconductor (Zoho-backed) |
| Mohali | Government fab | Strategic sovereign fab capability | SCL Mohali (PSU, ₹4,500 Cr modernisation) |
6. The investment thesis: why now?
Semiconductor startups in India spent most of the 2010s invisible to institutional capital: bootstrapped, grant-funded, or quietly acquired by multinationals before they could scale. What changed?
The convergence of four forces
- The China+1 imperative. Supply chain diversification has become a board-level priority for global OEMs and semiconductor companies. India is large, democratic and English-speaking, with elite technical talent, which makes it a natural destination for R&D expansion and foundry qualification. This creates market pull for Indian-origin chips.
- The DLI de-risking effect. Government DLI support does not replace VC capital; it de-risks the early tape-out. A startup with DLI backing has validated technical credibility and subsidised its most capital-intensive phase, which makes later private rounds more investable.
- IIT and IISc talent maturation. The current wave of founders are not fresh PhD graduates. They are engineers with 10 to 20 years of experience at Intel, Texas Instruments, Qualcomm or Infineon: people who have shipped silicon at production scale and know what it takes. The risk profile is very different from a decade ago.
- The GenAI infrastructure build-out. The global surge in AI compute demand has opened commercial space for edge inference, vision and power management chips that did not exist at scale five years ago. Indian startups such as Netrasemi (vision SoC), Morphing Machines (reconfigurable AI processor) and Calligo (RISC-V HPC co-processor) are targeting these exact inflection points.
22% of Indian VCs identified semiconductors as their top investment priority for 2025, as reported. For a sector that was barely on the radar in 2022, that is a remarkable shift in capital allocation intent.
7. Honest assessment: what still needs to change
India's semiconductor momentum is real, but so are the structural gaps. A rigorous analysis has to name both.
The gaps
- Analog and mixed-signal IP. India's design talent pool is concentrated in digital design. Analog IC design (precision amplifiers, data converters, power management and RF front ends) needs a different kind of expertise that takes decades to accumulate. Most Indian startups designing analog-heavy products still rely on third-party IP or expatriate talent.
- Manufacturing intelligence. Building a fab is not the same as running one competitively. The Tata-PSMC fab's success will depend on reaching target yields on 28nm logic within 6 to 12 months of first production. Yield ramp is where semiconductor manufacturing bets are won or lost. India has limited institutional knowledge here and will need to import it.
- The tape-out to revenue gap. For the 23 DLI-sanctioned startups, the critical next milestone is not more tape-outs; it is first commercial revenue. A chip that passes silicon validation still needs a customer design-in, a qualification cycle and a volume ramp. For automotive or industrial applications that takes two to three years at minimum, and many of these companies are only starting that journey.
- Business and go-to-market talent. The Endiya Partners 2026 semiconductor report identifies business talent as a critical gap alongside analog IP and manufacturing intelligence. India has world-class engineers but far fewer semiconductor product managers, field applications engineers and go-to-market executives with commercial silicon experience.
- Ecosystem density. A mature semiconductor cluster is not just design companies. It includes EDA vendors, IP licensors, packaging houses, test equipment providers, substrate makers and a deep talent pool in all of them. India is building the top of the stack; the supporting layers are still thin.
8. The 18-month scorecard: what to watch
The Endiya Partners IESA Vision Summit 2026 report describes the next 18 months as the most important test of India's semiconductor ambitions. Here is the scorecard that will show whether this moment is real or aspirational:
| Milestone | Why it matters | Target window |
|---|---|---|
| Tata-PSMC fab first silicon | Demonstrates India can operate a commercial fab at all | Dec 2026 |
| Tata-PSMC yield ramp (28nm/40nm) | The actual competitive test: yields determine economics | Q2 to Q3 2027 |
| 3 OSAT facilities at volume | ATMP scale validates India's packaging ambitions | 2026 to 2027 |
| DLI startups: first commercial revenue | Tape-out to revenue is the value creation test | 2026 to 2027 |
| Netrasemi SoC production ramp | First mass-market Indian edge AI chip in real deployment | H2 2026 |
| Mindgrove Vision SoC commercial wins | Second-generation product success validates repeatability | 2026 to 2027 |
| ISM 2.0 equipment/IP programme | Equipment, materials and IP are the long-term moat | FY 2026-27 |
9. The bigger picture: strategic sovereignty and global position
India's semiconductor push is ultimately not just an industrial policy story; it is a geopolitical one. The Economic Survey 2025 to 2026 explicitly frames semiconductors as the backbone of energy networks, financial markets and telecommunications. A country that designs its own chips has fewer strategic vulnerabilities and greater economic resilience.
For global semiconductor companies, India is at once a talent source, a market and an increasingly attractive risk-diversification destination. Qualcomm's 2nm tape-out at TSMC in February 2026 was reported to have been done with Indian design teams. AMD and Intel continue to expand their India R&D centres, and Arm has a growing design footprint in Hyderabad and Bengaluru.
The deeper shift, however, is the emergence of Indian-founded, Indian-headquartered semiconductor companies that design for global markets. These are not IT services firms with chip engineering departments; they are product companies with their own IP, their own roadmaps and their own commercial destiny. That is new, and it now looks irreversible.
India will not replace Taiwan in semiconductor manufacturing this decade. That is not the goal. The goal is to build enough indigenous capability that India is never again a passive bystander when the world's chip supply chains are stress-tested.
FAQ
What is the DLI scheme?
The Design Linked Incentive scheme, run by the India Semiconductor Mission under MeitY, supports Indian chip design companies with EDA tools, MPW fabrication slots and IP, plus incentives of 4 to 6% of net sales for five years, capped at ₹30 crore per applicant.
Does India make chips today?
India assembles and tests chips (Micron Sanand began commercial production in February 2026, and CG Semi runs an OSAT pilot line) and the government's SCL Mohali fab runs mature nodes. The first commercial wafer fab, Tata-PSMC at Dholera, targets first output in December 2026.
Which Indian chip startups are furthest along?
From this list, Netrasemi (12nm vision SoC, Series A), Mindgrove (commercial RISC-V MCU) and InCore (licensable RISC-V cores) are among the most visible, with Saankhya Labs already part of Tejas Networks.
What is the biggest risk?
Converting tape-outs into revenue and fab capacity into competitive yield. Both take years and depend on skills India is still building: commercial go-to-market for startups and yield engineering for fabs.
Conclusion: from talent exporter to IP builder
India's semiconductor story is one of structural transformation: from a country that supplies engineering labour to one that creates semiconductor intellectual property and, increasingly, the physical infrastructure to manufacture it. The numbers are modest by global standards. $50 million in startup funding is a rounding error in Taiwan's ecosystem, and Tata's 28nm fab is several generations behind TSMC's leading edge.
But the direction is clear and the foundations are sound. The talent base exists. The policy architecture is in place and deepening with ISM 2.0. The infrastructure is coming. And a first generation of technically credible, investor-backed, commercially focused chip startups is moving from prototype to revenue.
India's semiconductor moment is not a media narrative. It is an engineering and business reality being built one tape-out, one design win and one wafer start at a time.
Sources: India Semiconductor Mission (ISM/MeitY), DLI scheme public disclosures, PIB press releases, Inc42, YourStory, Endiya Partners IESA Vision Summit 2026 report, India Briefing, IBEF, SEMICON India 2025 proceedings, Business Standard (Micron Sanand inauguration, 28 February 2026).
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