EMIB and CoWoS are the two leading ways to join several chiplets and HBM stacks in one package. Intel's EMIB (Embedded Multi-die Interconnect Bridge) embeds small silicon bridges in an organic substrate only where two dies meet. TSMC's CoWoS (Chip on Wafer on Substrate) places all the dies on a large interposer that carries the wiring between them. In short, EMIB saves silicon and cost and eases warpage, while CoWoS has been the proven route to the highest memory bandwidth, which is why it carries most of today's AI accelerators.
Key takeaways
- Both are 2.5D packaging: dies sit side by side and talk through dense wiring, rather than being stacked on top of each other (3D).
- EMIB uses a silicon bridge of a few millimetres per die-to-die edge, embedded in the substrate. CoWoS-S uses one silicon interposer under every die; CoWoS-L and CoWoS-R swap that for RDL interposers, with or without local silicon bridges.
- CoWoS powers NVIDIA A100, H100 and Blackwell, AMD MI300 and many custom AI chips. EMIB ships in Intel Xeon (Sapphire Rapids and later), Ponte Vecchio and Altera Agilex FPGAs.
- TSMC CoWoS capacity was the main supply bottleneck for AI accelerators in 2024 and 2025, which made EMIB a more serious alternative for outside customers.
- The two are converging: CoWoS-L uses local bridges, and Intel's EMIB-T adds through-silicon vias to the bridge.
The comparison card below summarises the two approaches side by side.
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No large interposer Small Si bridge (~5×4 mm) embedded in substrate, die-to-die zone only
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Higher yield potential Smaller bridge die = lower defect probability; substrate scales independently
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Lower warpage risk Organic substrate CTE closer to PCB; no full-wafer silicon mismatch
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Scalable multi-die layout Multiple bridges can be placed wherever high-bandwidth die-to-die links are needed
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Large silicon interposer Passive Si interposer under all chiplets (CoWoS-S); CoWoS-R uses an organic RDL interposer, CoWoS-L an RDL interposer with local Si bridges
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Ultra-high interconnect density Fine interposer wiring (~9 µm RDL, as first published) enables very high die-to-HBM bandwidth (3.35 TB/s on an H100 SXM)
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Higher warpage risk CTE mismatch between large Si interposer and organic substrate drives warpage at reflow
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Capacity-constrained supply CoWoS capacity at TSMC was widely reported as the main bottleneck for AI accelerator supply in 2024–25
| Parameter | Intel EMIB | TSMC CoWoS | Edge |
|---|---|---|---|
| Interconnect pitchEMIB bump pitch vs CoWoS wiring | ~55 µm (gen 1), 45 µm (gen 2) | ~9 µm (RDL, as first published) | CoWoS |
| Package heightz-dimension | Typically lower | Taller (extra Si layer) | EMIB |
| Silicon area efficiencyrelative to die count | High (bridge <0.2% of pkg, est.) | Low (interposer ~100% of pkg) | EMIB |
| Max aggregate bandwidthper package | ~3.2 TB/s (Ponte Vecchio, Max 1550) | ~3.35 TB/s (H100 SXM) | CoWoS |
| Warpage riskat reflow | Lower | Higher | EMIB |
| Foundry dependencypackaging lock-in | Intel internal / IFS | TSMC only | Context |
| Known deploymentsproduction 2023–2025 | Ponte Vecchio, Sapphire Rapids, Agilex FPGAs | A100, H100, MI300X, Blackwell | CoWoS |
How EMIB works
An EMIB bridge is a small piece of silicon with several layers of fine wiring and no transistors. During substrate manufacture a cavity is formed and the bridge is placed in it, then covered by the substrate's build-up layers. When the dies are attached, the bumps along each die's edge land on the bridge, while the rest of each die's bumps land on ordinary substrate. Short, dense wires in the bridge carry the die-to-die traffic; power and slower signals go through the organic substrate as in any flip-chip package.
Intel's first EMIB generation used a 55 µm bump pitch at the bridge, and the second generation moved to 45 µm. Intel has since described EMIB-T, which adds through-silicon vias (TSVs) in the bridge so that power can be delivered straight up through it, aimed at HBM4 and UCIe-class die-to-die links. Intel papers at ECTC have reported still finer pitches on test vehicles.
How CoWoS works
In CoWoS-S, the original form, the dies are first bonded to a silicon interposer while it is still part of a wafer (the "chip on wafer" step). The interposer is passive: it has wiring layers and TSVs but no active transistors. The wafer is then thinned to expose the TSVs, diced, and the interposer with its dies is mounted on an organic substrate (the "on substrate" step). Because every die sits on the interposer, any die can be wired to any other with fine silicon wiring, and HBM stacks can sit right next to the logic die.
The limit is size. An interposer larger than one lithography reticle (roughly 26 mm by 33 mm, about 858 mm²) has to be made by stitching exposures, and big silicon interposers are expensive and prone to warpage. TSMC has answered with two variants:
| Variant | Interposer | Typical use |
|---|---|---|
| CoWoS-S | Silicon interposer with TSVs, passive | A100, H100, MI300X |
| CoWoS-R | Organic redistribution layer (RDL) interposer, no silicon | Cost-sensitive or very large packages where silicon wiring density is not needed everywhere |
| CoWoS-L | RDL interposer with embedded local silicon interconnect (LSI) bridges | NVIDIA Blackwell; very large multi-reticle packages |
CoWoS-L is conceptually close to EMIB: both put small silicon bridges only where dies meet. The difference is where the bridge lives. EMIB embeds it in the package substrate; CoWoS-L embeds it in a moulded RDL interposer that then sits on the substrate.
Worked example: silicon area
The silicon cost gap is easiest to see with numbers. These are illustrative, not a real product.
- A package holds one 800 mm² logic die and four HBM stacks of about 110 mm² each, with gaps between them. A CoWoS-S interposer to hold all of them needs to be roughly 1,700 mm², about two reticles.
- With EMIB, each HBM stack needs one bridge to the logic die. If each bridge is about 20 mm² (for example 5 mm by 4 mm, the size shown in the diagram above), four bridges total about 80 mm².
- That is roughly 20 times less bridge silicon than interposer silicon, and each small bridge is far more likely to be defect-free than one large interposer.
The trade-off is that the EMIB substrate must be built with cavities and the bridges must be placed accurately, and wiring outside the bridges is limited to organic substrate density.
Bandwidth: why CoWoS led for AI
AI accelerators are usually limited by memory bandwidth, and HBM delivers that bandwidth through a very wide interface (1,024 data bits per stack for HBM3, 2,048 for HBM4). Those thousands of wires must run a few millimetres from the HBM to the logic die. CoWoS has carried that interface in volume since the first HBM GPUs, and its ecosystem (TSMC wafers, HBM suppliers, OSAT partners) is what most AI chip designers built around. The 3.35 TB/s of an H100 SXM and the roughly 3.2 TB/s of Intel's Data Center GPU Max 1550 (Ponte Vecchio), shown in the table above, are both HBM figures; they show that EMIB can also carry an HBM interface at similar rates.
Warpage and reliability
Silicon expands with heat at about 2.6 to 3 ppm per °C; an organic substrate expands at roughly 10 to 17 ppm per °C, depending on the material. A large silicon interposer bonded to an organic substrate therefore bends as the package heats and cools during reflow and in use. The bigger the interposer, the larger the warpage, the harder assembly becomes and the higher the stress on bumps. EMIB keeps the silicon small, which is a large part of its warpage advantage. CoWoS-L and CoWoS-R reduce the problem on TSMC's side by replacing most of the silicon with RDL.
How to choose
| If your priority is | Leaning | Why |
|---|---|---|
| Proven HBM supply chain and highest bandwidth today | CoWoS | Largest base of production AI accelerators and HBM qualification |
| Lower silicon cost per package | EMIB | Small bridges instead of a large interposer |
| Very large packages (several reticles) | Either CoWoS-L or EMIB | Both avoid one giant silicon interposer |
| Packaging capacity outside TSMC | EMIB | Offered by Intel Foundry to outside customers |
| Dense any-to-any wiring between many dies | CoWoS-S | Silicon wiring under every die, not only at edges |
Common misconceptions
- "EMIB is 3D packaging." It is 2.5D. Intel's 3D stacking technology is Foveros, which Ponte Vecchio uses together with EMIB.
- "CoWoS-L has an active interposer." It does not. Its local silicon bridges and RDL are passive wiring, like CoWoS-S.
- "Finer bump pitch is the whole story." Bandwidth also depends on how many wires fit along each die edge, signalling rate and the die-to-die interface protocol (for example UCIe).
FAQ
Can a non-Intel chip use EMIB?
Yes. Intel Foundry offers EMIB packaging to outside customers, including for dies made at other foundries. In 2026 there were press reports that Google was considering EMIB for a future TPU; these were reports, not confirmed by either company at the time of writing.
Is CoWoS only for NVIDIA?
No. AMD, AWS, Google, Broadcom-designed custom chips and many others use CoWoS. NVIDIA has simply been its largest customer.
Which is cheaper?
EMIB generally uses far less silicon, so packaging cost per unit is expected to be lower, but published price comparisons are estimates from analysts rather than vendor figures.
What comes after both?
Hybrid bonding and 3D stacking (such as TSMC SoIC and Intel Foveros Direct) for the finest pitches, and glass or panel-level substrates for very large packages.
Sources and further reading
- Intel, EMIB and EMIB-T advanced packaging technology pages and ECTC papers.
- TSMC, 3DFabric and CoWoS technology overview.
- Tom's Hardware, reporting on Intel EMIB-T, 2025.
- NVIDIA H100 and Intel Data Center GPU Max 1550 product specifications (memory bandwidth figures).
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