ASIC and FPGA Verification: A Guide to Component Modeling (Book)

ASIC and FPGA Verification: A Guide to Component Modeling by Richard Munden is a practical book on writing simulation models of the off-the-shelf chips that sit next to your ASIC or FPGA on a board. It teaches how to build VHDL models with the VITAL standard, how to back-annotate timing with SDF, and how to use those models to verify a whole board, not just one device. If you need to simulate multi-chip digital designs with real timing, it is one of the few books written for exactly that job.

ASIC and FPGA Verification: A Guide to Component Modeling (Systems on Silicon)
by Richard Munden, Morgan Kaufmann, 2004, 336 pages, ISBN 0125105819

The book opens with a line that sums up its case: "As large and complex as today's FPGAs are, they always end up on a board..." (more)

Key takeaways

• An FPGA or ASIC that passes its own testbench can still fail on the board, because of the memories, buffers, PHYs and controllers around it.
• Board-level simulation needs component models with correct logic and correct timing: propagation delays, setup and hold checks, pulse width checks.
• The book uses VHDL with VITAL (IEEE Std 1076.4) for the models and SDF (Standard Delay Format, IEEE Std 1497) for timing back-annotation.
• It gives a clearly defined methodology and many example models, and was described as the first book to teach this subject as a whole.
• The author is associated with the Free Model Foundry, an effort to share interoperable component models.

Why component modelling matters

Most verification books focus on the device you are designing. In practice, a large share of board bring-up problems sit at the interfaces: an SDRAM that needs a different CAS latency, a level shifter that adds 3 ns you did not budget, a flash part whose hold time is longer than your FPGA's output hold. You only find these in simulation if you have models of those parts that behave and time like the real silicon.

Board-level simulation remains hard because such models are often missing, incomplete, or written in a style that does not work in your simulator. Munden's argument is that the industry can only make system simulation practical if model writers follow common standards and conventions, so that a model from one source drops into any testbench.

What a good component model contains

Part of the model	What it does	Example
Functional behaviour	Logic of the device, written at a level that simulates fast	Read and write cycles of a memory
Path delays	Pin-to-pin delays from input to output, often min:typ:max	Clock to Q delay of a register
Timing checks	Flags violations of setup, hold, recovery, pulse width	Data changes too close to the clock edge
Glitch handling	Decides what the output does when inputs change faster than the delay	Output glitch detection variables in VITAL
Back-annotation hooks	Generics or specify parameters that SDF can overwrite	Datasheet values loaded per speed grade

Topics the book covers

Key phrases from the book give a good picture of its depth: path delay section, negative timing constraints, skew violation, Free Model Foundry, output glitch detection variables, and VITAL memory modelling (more...). Negative timing constraints deserve a mention: some devices have a negative setup or hold time because of internal delays, and a model has to handle this without producing false violations, which is a subtle part of VITAL.

A worked example: pin-to-pin timing in a model

The book's models are VHDL with VITAL. The same idea exists in Verilog as a specify block, which many readers know better. The model below is a D flip-flop with a rise delay of 2.0 ns, a fall delay of 3.0 ns, a 1.0 ns setup check and a 0.5 ns hold check. All values are illustrative, not from a real datasheet. In a real flow an SDF file would overwrite them per speed grade.

`timescale 1ns/1ps
// Component model of a D flip-flop with pin-to-pin timing.
// Delays are illustrative.
module dff_model (input wire clk, input wire d, output reg q);
  reg notifier;
  initial q = 1'b0;
  always @(posedge clk) q <= d;
  specify
    (posedge clk => (q +: d)) = (2.0, 3.0);  // rise 2.0 ns, fall 3.0 ns
    $setup(d, posedge clk, 1.0, notifier);
    $hold(posedge clk, d, 0.5, notifier);
  endspecify
endmodule

With a 20 ns clock (rising edges at 10, 30 and 50 ns), d set to 1 at 5 ns and back to 0 at 25 ns, the simulation shows:

Clock edge	d at the edge	q changes at	Delay applied
10 ns	1	12 ns (0 to 1)	Rise, 2.0 ns
30 ns	0	33 ns (1 to 0)	Fall, 3.0 ns
50 ns	0	No change	None

A zero-delay RTL model would have changed q at 10 and 30 ns exactly. On a board where a downstream device samples q 2.5 ns after the clock, the zero-delay model says the falling data is captured correctly; the timed model shows the old value is still present at 32.5 ns. That is the class of bug component models exist to catch.

The equivalent SDF entry for a speed grade would look like this, with min:typ:max values that replace the defaults at load time:

(CELL (CELLTYPE "dff_model") (INSTANCE u_flash_if)
  (DELAY (ABSOLUTE
    (IOPATH (posedge clk) q (1.6:2.0:2.6) (2.4:3.0:3.9))))
  (TIMINGCHECK
    (SETUP d (posedge clk) (1.0))
    (HOLD  d (posedge clk) (0.5))))

Reviews

Randy Harr of Sevni Technology wrote that verifying boards and larger systems through simulation is still very difficult, that the biggest missing ingredient is the availability of IC component models, and that the book shows how to use VITAL and related conventions in VHDL to build interoperable, reusable models. In his view, only by adopting the standards and practices in the book can the industry make system simulation feasible.

Hardy Pottinger of the University of Missouri-Rolla described it as an excellent reference for anyone writing component models for board-level verification, and as a much needed introduction to SDF and VITAL for timing simulation.

Book description

Richard Munden shows how to create and use simulation models for verifying ASIC and FPGA designs, and board-level designs that use off-the-shelf digital components. The models follow the VHDL/VITAL standard and include the timing constraints and propagation delays needed for accurate verification of digital designs.

The book illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system, and is a valuable resource for any designer who simulates multi-chip digital designs.

• Provides numerous models and a clearly defined methodology for board-level simulation.
• Covers modelling for verification of both logic and timing.
• Described by the publisher as the first book to collect and teach techniques for using VHDL to model off-the-shelf or IP digital components for FPGA and board-level verification.

Who should read it

• FPGA engineers who own board bring-up and want to simulate the memories and peripherals around their device.
• Verification engineers building system-level or board-level testbenches.
• Model writers at component vendors who publish VHDL or Verilog models for customers.
• Readers who work only in Verilog or SystemVerilog will still find the timing concepts useful, but the code is VHDL.

Common mistakes in board-level simulation

• Zero-delay models everywhere: functional checks pass, interface timing is never tested.
• Only typical delays: run min and max corners; hold problems show at min, setup problems at max.
• Timing checks switched off to silence warnings: a violation message is the model doing its job.
• Models that do not match the part: check the model revision against the datasheet revision and speed grade.

FAQ

What is VITAL?

VITAL (VHDL Initiative Towards ASIC Libraries) is IEEE Std 1076.4. It defines packages and a modelling style for VHDL cells and components so that timing can be back-annotated from SDF in a standard way.

Is the book still relevant now that most teams use SystemVerilog?

Yes for the concepts: path delays, timing checks, negative constraints and SDF annotation work the same way in Verilog specify blocks. The VHDL code itself is most useful if your models or your vendor's models are VHDL.

Is it a free e-book?

No. It is a commercial book from Morgan Kaufmann (Elsevier), available in print and as an e-book through the usual sellers.