Showing posts with label Delays. Show all posts
Showing posts with label Delays. Show all posts

Delays in ASIC/VLSI design

Source Delay/Latency, Network Delay/Latency, Insertion Delay, Transition Delay/Slew, Path Delay, Net delay, Wire delay, Interconnect delay, Propagation Delay, Phase Delay, Cell Delay, Intrinsic Delay, Extrinsic Delay, Input Delay, Output Delay, Exit Delay, Latency (Pre/post CTS), Uncertainty (Pre/Post CTS), Unateness: Positive unateness, negative unateness, Jitter: PLL jitter, clock jitter.

These terms are explained in good detail @

Types of Delays

Intrinsic device delay: Time taken for the cell to change state due to a change on the input pins.
Interconnect delay: Delay due to wires. Dependent on layout. Smaller dimensions means more resistance. Making the wires "taller" leads to more capacitance.

• The total delay is the sum of the gate delay and the interconnect delay. Delay is mostly determined by the layout (placement) but varies with temperature, voltage and process.
• At above 0.5 micron interconnect delays are 20% of the path delay.
With present technologies it is from 40 to 60%. Thus delays are less predictable.
• Delays are even becoming a function of cross talk.