Delays in ASIC/VLSI design

Source Delay/Latency, Network Delay/Latency, Insertion Delay, Transition Delay/Slew, Path Delay, Net delay, Wire delay, Interconnect delay, Propagation Delay, Phase Delay, Cell Delay, Intrinsic Delay, Extrinsic Delay, Input Delay, Output Delay, Exit Delay, Latency (Pre/post CTS), Uncertainty (Pre/Post CTS), Unateness: Positive unateness, negative unateness, Jitter: PLL jitter, clock jitter.

These terms are explained in good detail @ http://vlsifaq.blogspot.com/