Delays in ASIC/VLSI design

Written by
Source Delay/Latency, Network Delay/Latency, Insertion Delay, Transition Delay/Slew, Path Delay, Net delay, Wire delay, Interconnect delay, Propagation Delay, Phase Delay, Cell Delay, Intrinsic Delay, Extrinsic Delay, Input Delay, Output Delay, Exit Delay, Latency (Pre/post CTS), Uncertainty (Pre/Post CTS), Unateness: Positive unateness, negative unateness, Jitter: PLL jitter, clock jitter.

These terms are explained in good detail @

Post a Comment


Your comments will be moderated before it can appear here. Win prizes for being an engaged reader.

Post a Comment (0)

#buttons=(Ok, Go it!) #days=(20)

Our website uses cookies to enhance your experience. Learn more
Ok, Go it!