Displaying posts in the categorySimulation
Simulation articles
Verilog
X-propagation is the way an unknown value, written as X in Verilog and SystemVerilog, spreads from its source through the logic of a design during simulation. The danger is that RTL simulation handles X inconsistently: some constructs hide an X and turn it into a clean 0 or 1 (X-optimism), while others turn known values into X (X-pessimism). Optimism can hide real bugs until silicon, and pessimism wastes debug time on failures that real hardware…
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Murugavel Ganesan
January 07, 2024
Verification
Zero-delay simulation runs a gate-level netlist with every gate and wire delay set to zero, so it checks that the synthesised logic does the right thing without checking when it does it. Use it early, after synthesis and before SDF-annotated timing simulation, to catch functional problems in the netlist quickly: wrong connectivity, reset and initialisation issues, X-propagation, and scan or test-mode behaviour. It cannot find setup or hold viola…
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Murugavel Ganesan
November 28, 2023
Verilog
Unit delay simulation gives every gate, and usually every flip-flop clock-to-output path, the same small delay of one time unit instead of its real delay. It is used mainly in gate-level simulation of a synthesised netlist before accurate timing is available, because it removes the race conditions that zero-delay netlist simulation suffers from, shows the order in which signals settle and exposes glitches. It does not check timing; that remains …
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Murugavel Ganesan
November 27, 2023
VHDL
The best free HDL simulators today are Icarus Verilog and Verilator for Verilog and SystemVerilog, and GHDL and NVC for VHDL. All four are open source and actively maintained. If you need a mixed-language or full SystemVerilog simulator at no cost, the free editions that ship with FPGA vendor tools (AMD Vivado's built-in simulator and Questa Altera FPGA Starter Edition) and the browser-based EDA Playground are the practical options. Free H…
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Murugavel Ganesan
March 19, 2023
Verification
This functional verification interview question asks you to choose between keeping both a functional and a timing simulator, or dropping one of them to buy more compute. A strong answer keeps functional simulation, because it is where most bugs are found and fixed cheaply, and treats timing simulation and the FPGA board as complementary ways to catch timing problems. In practice most candidates should choose FTB, consider FCB, and reject TCB, …
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Murugavel Ganesan
June 08, 2020
Simulation
This presentation will go over some of the common issues encountered when setting up performing circuit simulation of high speed serial designs. Topics will include s-parameter passivity and causality, frequency sampling and bandwidth and how they relate to simulation accuracy, model concatenation, and correlation between the time and frequency domains. This webcast is Hosted by EDN and Sponsored by ANSYS. Register Now - Click Here Present…
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Murugavel Ganesan
March 23, 2011
Verification
Acceleration, Emulation, and FPGA prototypes are most talked about these days and each has a distinctive role to play. In our earlier post we reflected on the Cadence rollout of Palladium XP, a verification computing platform that unifies acceleration capabilities from the Incisive Xtreme product line with Incisive Palladium emulation, incorporating some of the strongest capabilities from each platform. You can read the press release her…
Verification
Cadence Design Systems, Inc. has announced a fully integrated high-performance verification computing platform, called Palladium XP, that unifies simulation, acceleration and emulation into a single verification environment. Developed to support next-generation designs, the highly scalable Palladium XP verification computing platform lets design and verification teams bring up their hardware/ software environment faster and produce better qualit…
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Murugavel Ganesan
April 27, 2010
VHDL
This article provides a comprehensive methodology that highlights the best practices for mixed-language design integration and automatically comes up with an option for designers to select the optimal method for integration. There are broadly five ways of making mixed-language connections. Pros and cons of each of these approaches and their comparison is described in terms of the usage scenarios, performance implications of using one versus t…
Verilog
Verilog2C++ is a Verilog to C++ translation program that translates a C++ class of a Verilog design using a cycle-accurate representation of each nets and registers. Verilog2C++ is about 10 times faster than other commercial simulators, but has only simple functions.
Verification
VN-Cover by TransEDA is a code and FSM coverage tool that identifies any unverified parts of a simulated HDL design. VN-Cover includes a comprehensive set of metrics, which include line, statement, branch, condition, path, toggle, triggering, signal trace and FSM state, arc and path. In addition, the tool offers advanced features such as Deglitch and Coverability Analysis option, aimed at increasing measured coverage accuracy. VN-Cover seamles…
Simulation
ESL design and verification is an emerging electronic design methodology that focuses on the higher abstraction level. The basic essence is to model the behavior of the entire system using a high-level language such as C, C++, SystemC or SystemC TLM-2.0. ESL is evolving into a set of methodologies that enable embedded system design, hardware verification, debugging through to the hardware and software implementation of custom SoC, and Architectu…
VHDL
ModelSim PE Student Edition was a free, size-limited version of Mentor Graphics' ModelSim HDL simulator for students running VHDL or Verilog coursework on Windows. This post, first published in 2010, records what the Student Edition offered and how it was installed. As of November 2026, Siemens (which now owns the former Mentor Graphics tools) states that the Student Edition is not currently available for download, so the update below lists …
Tutorials
In this article we will see how to create a simple Tcl script that tests for certain values on a signal and then adds bookmarks that zoom the Wave window when that value exists. Bookmarks allow you to save a particular zoom range and scroll position in the Wave window. The Tcl script also creates buttons in the Main window that call these bookmarks. 1. Create the script. a. In a text editor, open a new file and enter the following lines: p…
Simulation
Fedora Electronic Lab (FEL) was a Fedora Linux spin that bundled open-source electronic design automation (EDA) tools for chip and board design into one installable system. It set out to fix one big problem in the open-source community: there was no single provider of open-source EDA that worked for real-life design flows. FEL packaged simulators, layout tools, HDL utilities, standard cell libraries and embedded tool chains so that a designer co…
