Webinar watch: Accelerating Time-To-SI-Closure

Webinar:Accelerating Time-To-SI-Closure
Date:Tuesday, March 31, 2009
Time: 11 amPT / 2 pm ET
Duration: 60Minutes

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Liveattendees who also submit the feedback form will be eligible to win a FREE 8GBiPod Touch (value approx. $250).

Accelerating Time-to-SI –Closure:
Unmanagedtiming-ECOs during the final stages of design can severely impact your tapeout schedule. Join our experts to learn how to usesignoff-driven SI-closure to keep your schedule on track and your performanceon target. This is the first in IC Compiler 2009 Webinar Series highlightingkey technologies for speeding design closure. Up-coming topics includeplacement-congestion minimization, power-rail design and in-design physicalverification.

Dr. Henry Sheng
Dr. Henry Sheng is R&D Group Director for Design Closure in ICCompiler. Henry and his organization are responsible for implementationextraction, timing and signal integrity, as well as Multi-corner Multi-mode(MCMM) and post-route closure. He has been with Synopsys since 1996. Henryholds a Ph.D. degree in Electrical Engineering and Computer Science from theUniversity of California, Berkeley.

Dr. Jinan Lou
Dr. JinanLou received his B.S. degree in Computer Engineering and Computer Science, M.S.and Ph.D. degrees in Computer Engineering, from University of SouthernCalifornia, Los Angeles, in 1993, 1995 and 1999, respectively. He is currentlya Principal Engineer at Synopsys. His research interests include physicaloptimization, layout driven logic synthesis and post-layout optimization fordeep-submicron technologies.

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