Interview Questions
sequential circuit
What is the smallest value for the ROM's contamination delay that ensures the necessary timing spec…
Sequential Circuits
sequential circuit
What is the smallest clock period for which the circuit still operates correctly? By removing the pair of i…
Interview Questions
sequential circuit
Calculate timing parameters for the system as a whole taking into account d1 and d2. Don't make any assumption abou…
Sequential Circuits
sequential circuit
Calculate the timing parameters (tS, tH, tCD, tPD, tCLK) for this system as a whole.
TCP
TCP Q&A
What is TCP? Transmission Control Protocol ( TCP ) provides a reliable byte-stream transfer service between two endpoin…
IP
IP Fragmentation Q&A
What is meant by IP fragmentation? The breaking up of a single IP datagram into two or more IP datagrams of smaller siz…
RARP
RARP Q&A
What is RARP? Reverse Address Resolution Protocol (RARP) is a network protocol used to resolve a data link layer addres…
ARP
ARP Q&A
What is ARP? Address Resolution Protocol (ARP) is a network protocol, which maps a network layer protocol address to a …
Ethernet
Ethernet Q&A
What is Ethernet? Ethernet is a Local Area Network (LAN) cabling and signaling specification for baseband networks. Eth…
Algorithms
Algorithms and High-Level Models
For designs with significant control flow, algorithms can be described in software languages, flowcharts, abstract stat…
Coding
“behavioural model” & “structural model”
The phrases "behavioural model" and "structural model" are commonly used for what we'll call &q…
Design
Basic aspects of a typical digital design flow...
Requirements Description of what the customer wants Algorithm Functional description of computation. Probably not synth…
Guidelines
General FPGA based design Guidelines
Based on past experience i had with FPGAs... Flip-flops are almost free in FPGAs, the reason is that in FPGAs, the area…
Synchronization
Asynchronous in a synchronous world - Part 2
Performing static timing analysis is the process of verifying that every signal path in a design meets required clock-c…
Synchronization
Asynchronous in a synchronous world - Part 1
The purpose of synchronizing signals is to protect downstream logic from the metastable state of the first flip-flop in…
Synchronization
Asynchronous in a synchronous world - Introduction
I am composing this article to explore various aspects of clock and data synchronization. The first part of the article…
Coding
Verilog code to detect if a 64bit pattern can be expressed using power of 2
module pat_det ( data_in, patDetected ); input [31:0] data_in; output patDetected; wire [4:0] patSum = data_in[0] + dat…
Verilog
Verilog Shift Register with Test Bench
A Verilog module for a 4-bit shift register with a testbench. The shift register will be a simple serial-in, serial-ou…