Fifo depth calculation
A First-In-First-Out (FIFO) depth calculation is a crucial aspect of designing and implementing FIFO buffers or queuing…
A First-In-First-Out (FIFO) depth calculation is a crucial aspect of designing and implementing FIFO buffers or queuing…
Advanced Microcontroller Bus Architecture (AMBA): Description: The AMBA™ on-chip interconnect system is an established …
SOC interconnect bus: These buses are used within a chip to interconnect an different IP cores to the surrounding inter…
The Inter-IC bus, commonly known as the I²C ("eye-squared-see") bus, is a control bus that provides the commu…
HDLC is a bit-oriented, link layer protocol for the transmission of data over synchronous networks. It is an ISO standa…
Dynamic timing: The design is simulated in full timing mode. Not all possibilities tested as it is dependent on the inp…
Intrinsic device delay: Time taken for the cell to change state due to a change on the input pins. Interconnect delay: …
Clock Skew: Differences in clock signal arrival times across the chip are called clock skew. It is a fundamental design…
# Have you studied buses? What types? Ans: 1. Processor-Memory Bus, I/O Bus, System Bus, Backplane Bus. # Have you s…
Any electronic system that uses a CPU chip, but that is not a general-purpose workstation, desktop or laptop computer. …
You can think of tristate buffers as a way of turning a signal on and off. When the enable input at the top of the buff…
Multi-cycle functionality: It is a fundamental characteristic of synthesizable RTL code that the complete functionality…
Clock latency means, the number of clock pulses required by the ckt to give out the first output. Generally we will obs…
OR gate from 2:1 MUX: Assumptions: 's' is the select line for the mux. 'I0 and I1' be the input data li…
Verification: In order to verify the functional correctness of a design, one needs to capture the model of the behavior…
One of the most common, but unfortunate misuse of terminology is treating "load testing" and "stress tes…
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In the simplest form: FF1 - combo - FF2 ( this is how things look physically for our consideration) Tmin = Tclk2Q (F…
Check critical path and optimize it. Add more timing constraints (over constrain). pipeline the architecture to the max…
DFT: manufacturing defects like stuck at "0" or "1". test for set of rules followed during the init…
Advantges: used to save power by masking the clock to the flops. used in clock switching circuits. Reduces routing burd…
The setup time is the time the data inputs must be valid before the clock/strobe signal. tSU(chip-pin)= tSU(FF) - Tdela…
Wire loading models contain all the information required by compile to estimate interconnect wiring delays. A typical W…
What interrupts are active low in digital circuits? In digital circuits, an interrupt is a signal that causes the proce…
slack is defined as the difference between the reqd_arrival time of a signal & it's actual arrival time. It sho…
Normally polysilicon has more resistance compared to metal. For shorter distance we go with polysilicon keeping fabrica…
NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is normally three t…
The main diferrence between ASIC and FPGA based design is in the Back-end. In FPGAs there is not much activities in bac…
The path in digital circuits which is not associated with a clock, is known as default path. While considering and calc…
Coarse-grained architectures consist of fairly large logic blocks, often containing two or more look-up tables and two …