Synchronization
Asynchronous in a synchronous world - Part 2
Performing static timing analysis is the process of verifying that every signal path in a design meets required clock-c…
Showing posts from 2005
Synchronization
Asynchronous in a synchronous world - Part 1
The purpose of synchronizing signals is to protect downstream logic from the metastable state of the first flip-flop in…
Synchronization
Asynchronous in a synchronous world - Introduction
I am composing this article to explore various aspects of clock and data synchronization. The first part of the article…
Coding
Verilog code to detect if a 64bit pattern can be expressed using power of 2
module pat_det ( data_in, patDetected ); input [31:0] data_in; output patDetected; wire [4:0] patSum = data_in[0] + dat…
Coding
Verilog Shift Register with Test Bench
module shifter (result, value_in, direction, type, length); output [7:0] result; input [7:0] value_in; input direction;…
Verilog
Verilog Awareness
Differentiate between Inter assignment Delay and Inertial Delay ? What are the different State machine Styles ? Which i…
Verilog
Verilog Awareness
Consider a 2:1 mux , what will be the output F if the Select (sel) is "X" ? What is the difference between bl…
Jitter
Clock Jitter
Clock jitter is the deviation from the ideal timing of clock transition events. Because such deviation can be detriment…
Verilog
Verilog Blocking Vs Non Blocking, Myths and Facts
I know people who swear by blocking and some who swear by non-blocking. So here are some thoughts. There is very little…
Synthesis
Clock tree synthesis
Basics of Clock Tree Synthesis: The main idea is to balance the skew between endpoints. They are built with the followi…
Guidelines
Design Guidelines and Criteria for Digital Electronics
..apparently these pages on guidelines and criteria, are from NASA. I think this is a very nice article with good amoun…
State Machines
"Safe" and "Unsafe" state machines
"Safe" State Machines: If the number of states (N) is a power of 2 and you use a binary or gray-code encoding…
Metastability
Metastability
Metastability in electronic circuits Metastability is a phenomenon that occurs in digital circuits when an input signal…
Interview Questions
Synthesizable Verilog from behavioral constructs - 5
Delay statements, e.g. @(posedge clock), require careful attention if there are several in a row. If there are only del…
Interview Questions
Synthesizable Verilog from behavioral constructs - 4
When implementing Verilog tasks in modules, the best approach is to group tasks that have the same output signals into …
Interview Questions
synthesizable Verilog from behavioral constructs - 3
To modify a behavioural Verilog fork and join statement to make it synthesizable. Behavioural: command1; fork //…
Interview Questions
synthesizable Verilog from behavioral constructs - 2
Modifying a behavioural Verilog while statement to make it synthesizable. Behavioural: command1; while (x != 0) …
Interview Questions
synthesizable Verilog from behavioral constructs - 1
Modifying a behavioural Verilog wait statement to make it synthesizable. Behavioural: command1; wait (x != 0); c…
Digital
A nice site for basics on Digital Logic Design
http://www.allaboutcircuits.com/ , Look up Volume IV - Digital Summary of topics covered... Chapter 1: NUMERATION SYS…
Learning
1's complement and 2's complement
In digital logic design, one of the ways to represent negative numbers is by using signed number representation. One of…
Setup
negative setup and hold time
A negative setup and hold condition is a very interesting proposition in static timing analysis. Support for this type …
I2C
I2C Interview Questions
Question: What is the maximum distance of the I2C bus? This depends on the load of the bu s and the speed y…
Interview Questions
more questions
1. Given 2 4 bit nos, A= 1001, b= 1100 HOW DO YOU ExOR THEM using minimum number of gates? how do you nand them? …
Xor
Mux out of an XOR
Here is some background and a step to solve the problem: A set of {+, . , '} is functionally complete because every…
RTL Design
Design Interview questions
1.) You are adding 8 10-bit numbers. How many bits do you need for the result? 2.) You are adding two 2's-compleme…
Glitch
Glitch in a combinational circuit and the way to avoid that.
A glitch resistive transition means, it is not possible to have any intermediate momentary values during output transit…
For Loop
Why "FOR LOOP" is not advisable
Why "FOR LOOP" is not advisable to code in RTL eventhough it is synthesizable? I agree with this explanation.…
Setup
Setup Time & Hold Time - By popular demand
a) Generally speaking SETUP fixing is always DIFFICULT. This can be resolved by inserting buffers (as you mentioned) on…
Logic Density
Logic Density
Find the resource elements consumed during design stage that is before RTL coding.Is it necessarily needed to draw the …
Negative hold time
What is a Negative hold time?
Negative hold time is generally seen where a delay is already added in the data path inside the flop. This is usually d…
TOC
Test
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