Latch-based designs are sometimes used for high-speed digital circuits. One possible configuration places combinational logic between a pair of latches with opposite polarities (one latch is active high and the other is active low) that use the same clock signal. The two latches given below are intended to be used in such configuration. One of the two designs is an active high latch while the other is an active low latch. Additionally, you know that one of the two designs is a “bad” latch.
- Which of the two latches is active high and which is active low?
- Which of the two latches is the “bad” latch? Clearly justify your answer.