HDL Coding Guidelines - Part 3

  1. Language for modeling should be VHDL-87
  2. VHDL-93 keywords should not be used
  3. Verilog keywords should not be used
  4. SDF keywords should not be used
  5. IKOS keywords should not be used
  6. Allowable replacement characters are forbidden
  7. Tool specific types may not be used
  8. Configuration declarations must have the configuration name and the entity name in one line
  9. Never redefine standard operators, subprograms, attributes, and packages
  10. Design-internal references must use library work
  11. Bussed ports of width one are forbidden
  12. Carefully use real values with PN-generators
  13. Be aware of operating-system-specific features
  1. Bussed arithmetic objects use "downto" as their index orientation
  2. Comparison of arrays must be based on arrays of the same width
  3. Request external VHDL code suppliers to deliver used arithmetic packages
  4. Avoid homographs
  5. Where to use ieee.std_logic_arith and std_developerskit.synth_regpak
  6. Where to use std_logic_signed and std_logic_unsigned
  7. Take care of array widths for std_logic_arith operators
  8. Use conversion functions around arithmetic operators
Note that the restrictions listed below do not apply to pure simulation models and not to testbench models.
  1. Code for synthesis must match the synthesis subset
  2. Store package header and body into same file
  3. Default values for ports, signals, and variables may not be used
  4. Data types must be synthesizable
  5. Array ranges must be of type integer
  6. Integer type objects must be constrained with respect to to their range
  7. Use standard templates for clocked processes
  8. Generics must have type integer
  9. Order of generics in entity, component and instance must be the same
  10. Place port and generic maps at the component instantiation
  11. Instantiated component and entity name must be equal, incl. casing
  12. The sensitivity list for combinational processes must be complete
  13. Write variables before read in combinational logic
  14. Bit-wise association of arrays in port maps is not possible in presence of generics
  15. Embedding scripts as meta comments is not acceptable
  16. Use only standard meta comments
  17. Gate instantiation must be encapsulated by separate unit
  18. Requirements for resource sharing
Simulation Performance
  1. Use sensitivity lists instead of wait statements
  2. Minimize the number of signals of your sensitivity list
  3. Avoid unnecessary computations within loops
  4. Remove unnecessary code fragments
  5. EMC and transmission line effects need not be modeled
  6. Use abstract, compact coding style in testbench and simulation models
  7. Minimize the number of processes, signals, and signal assignments
  8. Replace signals by variables whenever possible
  9. Inhibit execution of statements where not necessary
  10. Divide large memories into blocks
  11. Avoid unnecessary repetition of function calls
  12. Avoid declaring constants within subprograms
  13. Always use deallocate(access_obj) to dereference allocated memory
Critical Constructs
  1. Do not use guarded signals, guarded assignments, and guarded expressions
  2. Do not use disconnect, register, and bus
  3. Do not use configuration specification (“hard binding”)
  4. Do not use port modes buffer and linkage
  5. Do not use blocks
  6. Avoid identifier hiding caused by loop index
  7. Global signals may be used for testing purposes only
  8. Recursive use of subprograms is forbidden
  9. Subprograms may not have any side effects
  10. Use only well tested functions for object-initialization purposes
  11. Be aware of the use of the attributes DELAYED, STABLE, QUIET, and TRANSACTION

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