HDL Coding Guidelines - Part 4

To Avoid common Errors
  1. A configuration declaration is needed for each architecture in the design
  2. Design-internal references must use library work
  3. Use selected names in binding indications and ’use’ clauses only
  4. Configuration must be in a separated file except the latest level of hierarchy
  5. All primary unit names must be unique in the project library
  6. Identifier casing should be uniform in all VHDL code
  7. Length of entity names should not exceed 32 characters
  8. An instance name must not contain the substring ’pfiller’
  9. Use unresolved data types if possible
  10. Hard/firm macros: Data types at ports: std_(u)logic(_vector)
  11. Generics must have type integer for synthesis
  12. Avoid feedthroughs
  13. Strength stripping should be performed on chip level
  14. Do not assign the value 'X'
  15. Asynchronous reset is mandatory for sequential processes
  16. Do not use internal three-state busses
  17. Use the predefined templates for component instantiation
  18. Refer to one edge of clock, only
  19. Do not use combinational feedback loops
  20. Global signals may be used for testing purposes only
  21. Use relative path names for files accessed through text-IO
  22. Binary file-IO may not be used
  23. In association lists of generic maps and port maps use named association
  24. VHDL-93 keywords should not be used
  25. Verilog keywords should not be used
  26. SDF keywords should not be used
  27. IKOS keywords should not be used
  28. Allowable replacement characters are forbidden
  29. Tool specific types may not be used
  30. Configuration declarations must have the configuration name and the entity name in one line for vimport
  31. Never redefine standard operators, subprograms, attributes, and packages
  32. Language for modeling is VHDL-87
  33. Comparison of arrays must be based on arrays of the same width
  34. Bussed arithmetic objects use "downto" as their index orientation
  35. Store package header and body into same file
  36. Default values for ports, signals, and variables may not be used
  37. Data types must be synthesizable
  38. Array ranges must be of type integer
  39. Integer type objects must be constrained with respect to to their range
  40. Use standard templates for clocked processes
  41. Generics must have type integer
  42. Order of generics in entity, component and instance must be the same
  43. Place port and generic maps at the component instantiation
  44. Instantiated component and entity name must be equal, incl. casing
  45. The sensitivity list for combinational processes must be complete
  46. Write variables before read in combinational logic
  47. Bit-wise association of arrays in port maps is not possible in presence of generics
  48. Embedding scripts as meta comments is not acceptable
  49. Use only standard meta comments
  50. Code for synthesis must match the synthesis subset
  51. Do not use disconnect, register, and bus
  52. Do not use port modes buffer and linkage
  53. Do not use configuration specification (“hard binding”)
  54. Do not use blocks
  55. Avoid identifier hiding caused by loop index
  56. Recursive use of subprograms is forbidden
  57. Do not use guarded signals, guarded assignments, and guarded expressions
  58. Trailing comments are only allowed for declarative lists

0/Post a Comment/Comments

Your comments will be moderated before it can appear here.

Previous Post Next Post