HDL Coding Guidelines - Part 6

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To Avoid common Warnings
  1. Store each VHDL unit into a separate file except package header and body
  2. Signal assignments for renaming purposes should be avoided
  3. The names of clocks and resets should be unique in the whole design
  4. Soft macros: Data types at ports: std_(u)logic(_vector)
  5. Avoid custom data types (e.g., multidimensional arrays, records, enumeration types)
  6. Avoid gated clocks unless absolutely necessary
  7. Avoid latches unless absolutely necessary
  8. All outputs of synchronous modules should be registered
  9. Process only one clock in RTL-units
  10. Do not use the value of type’left for initializing of a signal or variable during reset
  11. Avoid unused ports, busses must be split accordingly
  12. Avoid homographs
  13. Do not define a subprogram for a subtype only
  14. Comment each process, each subprogram and global aspects
  15. Processes should be labeled
  16. Aliases are not recommended
  17. Bussed ports of width one are forbidden
  18. Use case-statements instead of if-statements when the conditions are mutually exclusive
  19. All signals and variables should be read at least once
  20. Static ports should not exist
  21. Use a separate library clause for each declared resource library
  22. Use a separate use clause for each declared package
  23. Maximum line-length is 100 characters
  24. Order of ports in entity, component and instance should be the same
  25. Do not have unused signals
  26. Minimize the number of signals of your sensitivity list
  27. Avoid unnecessary computations within loops
  28. Use sensitivity lists instead of wait statements
  29. Subprograms may not have any side effects

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