HDL Coding Guidelines - Part 5


Critical Policies to Keep note!
  1. Balance clock to delta accuracy
  2. Pull-ups and pull-downs have to be modeled on chip level
  3. Communication between modules using text-IO is forbidden
  4. No characters with a lower rank than space may occur in text-IO
  5. Testbench and DUT should be compiled into the same library
  6. Asynchronous parts should be placed into separate entities
  7. VHDL units should take into account later floorplanning
  8. A FSM must be described in a separate entity/architecture pair
  9. Only verified VHDL code allowed for check-in
  10. Identifier naming must be based on English language
  11. Use meaningful identifier names
  12. Separate identifier components using underscores
  13. Instantiate the power pads for each power domain
  14. Gate instantiation must be encapsulated by separate unit
  15. Spend extensive efforts for documentation of interfaces
  16. Request external VHDL code suppliers to deliver used arithmetic packages
  17. Spacer cells needed between pads
  18. Signals that cross clock domains must be synchronized by synchronization cells
  19. Language for comments and code documentation is English
  20. Comments should be related to the lines of code below

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