Showing posts from February, 2010

LTE-Advanced Technology Introduction

Show Me the Next-Generation HDMI

A Lifecycle Approach to Quality Management

Designing Low Power, Multi-Primary Technology for Mobile Phone Displays

Major Benefits of IEEE-1149.7(Compact JTAG)

Checklist for Success with Multicore

Fast, Easy, and Flexible Power for System Designers

Processor Affinity or Bound Multiprocessing?

Evolving the Coverage-Driven Verification FlowEvolving the Coverage-Driven Verification Flow

Improve Project Success with Better Information

Challenges for the 28nm half node: Is the optical shrink dead?

Debug and Validation of High Performance Mixed Signal Designs

SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits

Patents database: An easy and cost effective way to perform reverse engineering for chip designers

Best Practices for Reducing Risk through Environmental Compliance Data Collection

Application Specific IP

Boosting RTL Verification with High-Level Synthesis

SDRAM Memory Systems: Architecture Overview and Design Verification

Getting Started with Android Development for Embedded Systems

Phase-locked loops (PLLs) Demystified

Diagnosing clock domain crossing errors in FPGAs

Fantastic failures

Digital Signal Processing: A Practical Guide

The Art of Debugging: Make it Fail

Single Chip Coherent Multiprocessing

Data Management for Hardware Design Teams

e Verification language is alive and well

Broadcom's smartphone on a chip

Intel meets its match in IBM

Formal Verification: Theorem proving

Toyota Prius 2005: An Early Warning About Verification

Motivation: What else can we talk about verification?

Verification Sessions at DVcon 2010

Clock-Domain Crossing Verification Module

ModelSim PE Student Edition - Free HDL Simulation

Questa SV/AFV: Verification Methodology Kits

Questa Compatibility Matrix: Versions of Questa SV/AFV that work with different versions of other Mentor and open-source verification products

Design Verification Club (DVclub)

Delivering synthesizable verification IP for testbences

Toyota's woes: More technology, more complexity

Are latches really bad for a design?

Did the 3G auction happen in India on 14Jan?

iPad and the A4 chip

Load More Posts That is All