Showing posts with label PLL. Show all posts
Showing posts with label PLL. Show all posts

Phase-locked loops (PLLs) Demystified

Over the past decade, Phase-Locked Loops (PLLs) have become an integral part of the modern ASIC design. PLLs provide the clocks that sequence the operation of the various blocks on an ASIC chip as well as synthesize their communications. There are various types of PLLs targeting specific applications. Read this white paper to learn more about the types of PLLs and how they work in certain technologies.

Delay Locked Loop (DLL)

Why not a PLL:
PLLs have disadvantages that make their use in high-speed designs problematic, particularly when both high performance and high reliability are required. The PLL voltage-controlled oscillator (VCO) is the greatest source of problems. Variations in temperature, supply voltage, and manufacturing process affect the stability and operating performance of PLLs.

DLLs, however, are immune to these problems. A DLL in its simplest form inserts a variable delay line between the external clock and the internal clock. The clock tree distributes the clock to all registers and then back to the feedback pin of the DLL. The control circuit of the DLL adjusts the delays so that the rising edges of the feedback clock align with the input clock. Once the edges of the clocks are aligned, the DLL is locked, and both the input buffer delay and the clock skew are reduced to zero.

  • precision
  • stability
  • power management
  • noise sensitivity
  • jitter performance.

Check out this virtex data sheet...

Phase locked loop (PLL)

PLL stands for 'Phase-Locked Loop' and is basically a closed loop frequency control system, whose functioning is based on the phase sensitive detection of phase difference between the input and output signals of the controlled oscillator (CO).

For further info, click on the title...