Comparison of VHDL to Other Hardware Description Languages


VHDL Disadvantages
  • VHDL is verbose, complicated and confusing
  • Many different ways of saying the same thing
  • Constructs that have similar purpose have very different syntax (case vs. select)
  • Constructs that have similar syntax have very different semantics (variables vs signals)
  • Hardware that is synthesized is not always obvious (when is a signal a flip-flop vs latch vs combinational)
VHDL Advantages
  • VHDL supports unsynthesizable constructs that are useful in writing high-level models, testbenches and other non-hardware or non-synthesizable artifacts that we need in hardware design.
  • VHDL can be used throughout a large portion of the design process in different capacities, from specification to implementation to verification.
  • VHDL has static typechecking—many errors can be caught before synthesis and/or simulation.
  • VHDL has a rich collection of datatypes
  • VHDL is a full-featured language with a good module system (libraries and packages).
  • VHDL has a well-defined standard.
VHDL and Other Languages
  • VHDL vs Verilog
    • Verilog is a "simpler" language: smaller language, simple circuits are easier to write
    • VHDL has more features than Verilog
      • richer set of data types and strong type checking
      • VHDL offers more flexibility and expressivity for constructing large systems.
    • The VHDL Standard is more standard than the Verilog Standard
      • VHDL and Verilog have simulation-based semantics
      • Simulation vendors generally conform to VHDL standard
      • Some Verilog constructs don't simulate the same in different tools
    • VHDL is used more than Verilog in Europe and Japan
    • Verilog is used more than VHDL in North America
    • South-East Asia, India, South America - More Democratic
  • VHDL vs SystemC
    • System C looks like C —familiar syntax
    • C is often used in algorithmic descriptions of circuits, so why not try to use it for synthesizable code as well?
    • If you think VHDL is hard to synthesize, try C....
    • SystemC simulation is slower than advertised
  • VHDL vs Other Hardware Description Languages
    • Superlog: A proposed language that was based on Verilog and C. Basic core comes from Verilog. C-like extensions included to make language more expressive and powerful. Developed by the Co-Design company, but no longer under active development. Superlog has been superseded by SystemVerilog, see below.
    • SystemVerilog: A language originally proposed by Co-Design and now standardized by Accellera, an organization aimed at standardizing EDA languages. SystemVerilog is inspired by Verilog, Superlog, and System-C. SystemVerilog is a superset of Verilog aimed to support both high-level design and verification.
    • Esterelle: A language evolving from academia to commercial viability. Very clean semantics. Aimed at state machines, limited support for datapath operations.

Search capability added


Hello Readers:
We are happy to announce the introduction of a new search capability, visible on the right hand side column of this blog. You may use it to search for posts, articles posted on this blog only.

Thanks.

Difficulty of designing correct chips


"Everyone should get a lecture on why their first industrial design won't work in the field."

Here are few reasons getting a single system to work correctly for a few minutes in a university lab is much easier than getting thousands of systems to work correctly for months at a time in dozens of countries around the world.

1. You forgot to make your "unreachable" states transition to the initial (reset) state. Clock glitches, power surges, etc will occasionally cause your system to jump to a state that isn't defined or produce an illegal data value. When this happens, your design should reset itself, rather than crash or generatel illegal outputs.

2. You have internal registers that you can't access or test. If you can set a register you must have some way of reading the register from outside the chip.

3. Another chip controls your chip, and the other chip is buggy. All of your external control lines should be able to be disabled, so that you can isolate the source of problems.

4. Not enough decoupling capacitors on your board. The analog world is cruel and and unusual. Voltage spikes, current surges, crosstalk, etc can all corrupt the integrity of digital signals. Trying to save a few cents on decoupling capacitors can cause headaches and significant financial costs in the future.

5. You only tested your system in the lab, not in the real world. As a product, systems will need to run for months in the field, simulation and simple lab testing won't catch all of the weirdness of the real world.

6. You didn't adequately test the corner cases and boundary conditions. Every corner case is as important as the main case. Even if some weird event happens only once every six months, if you do not handle it correctly, the bug can still make your system unusable and unsellable.

Power Analysis and Power-Aware Design - Part 1


Importance of Power and Energy:
  1. Laptops, PDA, cell-phones, etc —obvious!
  2. For microprocessors in personal computers, every watt above 40W adds $1 to manufacturing cost.
  3. Approx 25% of operating expense of server farm goes to energy bills.
  4. Sandia Labs had to build a special sub-station when they took delivery of Teraflops massively parallel supercomputer (over 9000 Pentium Pros)
  5. High-speed microprocessors today can run so hot that they will damage themselves—Athlon reliability problems, Pentium 4 processor thermal throttling
  6. Future power viruses: cell phone viruses cause cell phone to run in full power mode
Most people talk about "power" reduction, but sometimes they mean "power" and sometimes "energy."
  1. Power minimization is usually about heat removal.
  2. Energy minimization is usually about battery life or energy costs.
Power Equations:
Power
= Switching Power+Shortcircuit Power+Leakage Power
Dynamic power = Switching Power+Shortcircuit Power
Static Power = Leakage Power
  1. Dynamic Power dependent upon clock speed
  2. Switching Power useful —charges/discharges transistors
  3. Short Circuit Power not useful —both N and P transistors are on
  4. Static Power independent of clock speed
  5. Leakage Power not useful —leaks around transistor
Dynamic power is proportional to how often signals change their value (switching)
  • Roughly 20% of signals switch during a clock cycle.
  • Need to take glitches into account when calculating activity factor. Glitches increase the activity factor.
  • Equations for dynamic power contain clock speed and activity factor.
Some power reduction techniques:
  • Analog
    • Parameters to work with:
      • capacitance for example, Silicon on Insulator (SOI)
      • resistance for example, copper wires
      • voltage low-voltage circuits
    • Techniques:
      • dual-VDD Two different supply voltages: high voltage for performance-critical portions of design, low voltage for remainder of circuit. Alternatively, can vary voltage over time: high voltage when running performance-critical software and low voltage when running software that is less sensitive to performance.
      • dual-Vt Two different threshold voltages: transistors with low threshold voltage for performance-critical portions of design (can switch more quickly, but more leakage power), transistors with high threshold voltage for remainder of circuit (switches more slowly, but reduces leakage power).
      • exotic circuits Special flops, latches, and combinational circuitry that run at a high frequency while minimizing power
      • adiabatic circuits Special circuitry that consumes power on 0 - 1 transitions, but not 1 - 0 transitions. These sacrifice performance for reduced power.
      • clock trees Up to 30% of total power can be consumed in clock generation and clock tree
  • Digital
    • Parameters to work with:
      • capacitance (number of gates)
      • activity factor
      • clock frequency
    • Techniques:
      • multiple clocks Put a high speed clock in performance-critical parts of design and a low speed clock for remainder of circuit
      • clock gating Turn off clock to portions of a chip when it's not being used
      • data encoding Gray coding vs one-hot vs fully encoded vs ...
      • glitch reduction Adjust circuit delays or add redundant circuitry to reduce or eliminate glitches.
      • asynchronous circuits Get rid of clocks altogether....

AGLOCO - Own the Internet


AGLOCO: The Internet's First Economic Network, that enables you to earn while you browse.

Today’s hottest Internet businesses are all about the power of social networks. Companies like MySpace, Facebook, and YouTube have become worth billions because businesses have realized that these social networks are generating huge advertising and marketing opportunities. As these social networks grow, the economic potential for its owners – and the advertisers who target the site’s users – is remarkable.

It was from this question that AGLOCO set out to create the Internet’s first Economic Network, harnessing the power of Internet-based social networks to directly benefit the Members who help to create the community.

Becoming a member of AGLOCO is as simple as completing a brief sign-up page (name, age, location and email address.). Once you’re a Member, you will be asked to then download the Viewbar™ software.
AGLOCO makes money for its Members in many ways
  • Search: Every time you use the Viewbar™ to do an Internet search, AGLOCO earns money from the search engine providers. (For example, Google pays as much as $0.10 on average for each search that is directed to its search engine.)
  • Advertising: The Viewbar™ itself displays ads that are targeted based upon the websites you’re visiting. When you click on an ad and make a purchase, AGLOCO receives a referral fee, which we pass on to our Members. (Please note: Individual members do not receive any compensation for clicking on ads in the Viewbar™, and the Viewbar™ can detect if someone is clicking ads in a fraudulent manner.)
  • Transaction commissions: Many major retailers pay commissions when you refer customers who make a purchase. AGLOCO collects that commission and passes it on to our members. (For example, Amazon pays an 8.5% commission to most websites who refer customers, and has cut deals for even larger percentages. The bigger the AGLOCO community, the better commission we can negotiate for our Members.)
  • Software distribution: Numerous software companies pay websites to encourage the download of new software releases (for example, Adobe’s Flash and Acrobat Reader software), and trial versions of new programs. AGLOCO members not only get access to the latest and coolest software, they get paid for it.
  • Service distribution: Many online service providers will look to the AGLOCO community as a source of new and active users for their services. (For example, eBay, Skype, and PayPal, among others, all pay fees to people who help them recruit new active users to their services)
  • Product distribution: When Members agree to use a product, such as cell phones, high-tech gadgets, office supplies, new credit cards or financial services, AGLOCO can collect referral fees. Some companies even offer special rebate and cash-back programs.
AGLOCO Members make money in four ways.
  • Members earn a monthly share of the AGLOCO revenue based on the use of the AGLOCO Viewbar™ that month.
  • Members earn part of the company based on the use of the AGLOCO Viewbar™ that month (currently a maximum of five hours are rewarded). Click here for details.
  • Members who use our referral system to help build the AGLOCO network will earn more. (AGLOCO only has significant value as a large network and people who help build it should be rewarded. – We also feel that the early users who told friends about YouTube or MySpace or even Google probably deserved something too, but no referral system was available to record their work).
  • Members will also get a share of any commissions AGLOCO gets when a Member purchases a product or service from an AGLOCO Sponsor company.
Why should I join now?
  • First, it costs nothing to Join and takes less than one minute.
  • Second, you can help build the AGLOCO community by recruiting new Members TODAY.
  • Right now, inviting your friends to join AGLOCO is as easy and productive as it will ever be – but you need to invite your friends before someone else beats you to them.
  • Remember, the bigger the AGLOCO community, the more attractive AGLOCO is to potential business partners and advertisers.
    • Recruit your friends and family by contacting them through email. (But remember we have a strict anti-spam policy.)
    • Use your blog and your existing social networks, such as MySpace and Facebook, to contact your friends and encourage them to join a new community that will actually let them earn money.
Be a part of the Internet’s first Member-Owned Economic Community.
Join AGLOCO - Own the Internet!

Delay Modelling and Coding Guidelines


Inertial delay models only propagate signals to an output after the input signals have remained unchanged (been stable) for a time period equal to or greater than the propagation delay of the model. If the time between two input changes is shorter than a procedural assignment delay, a continuous assignment delay, or gate delay, a previously scheduled but unrealized output event is replaced with a newly scheduled output event.

Transport delay models propagate all signals to an output after any input signals change. Scheduled output value changes are queued for transport delay models.

Modeling Guideline: Do not place delays on the LHS/RHS of blocking assignments to model combinational logic.
Testbench Guideline: Placing delays on the LHS of blocking assignments in a testbench is reasonable since the delay is just being used to time-space sequential input stimulus events, but on RHS is not. Placing a delay on the RHS of any blocking assignment is both confusing and a poor coding style.

Modeling Guideline:
Do not place delays on the LHS of nonblocking assignments to model combinational logic.
Testbench Guideline: Nonblocking assignments are less efficient to simulate than blocking assignments; therefore, in general, placing delays on the LHS of nonblocking
assignments for either modeling or testbench generation is discouraged.

Modeling Guideline:
Place delays on the RHS of nonblocking assignments only when trying to model transport output-propagation behavior. This coding style will accurately model delay lines and combinational logic with pure transport delays; however, this coding style generally causes slower simulations.
Testbench Guideline: This coding style is often used in testbenches when stimulus must be scheduled on future clock edges or after a set delay, while not blocking the
assignment of subsequent stimulus events in the same procedural block.

Modeling Guideline:
In general, do not place delays on the RHS of nonblocking assignments to model combinational logic. This coding style can be confusing and is not very simulation efficient. It is a common and sometimes useful practice to place delays on the RHS of nonblocking assignments to model clock-to-output behavior on sequential logic.
Testbench Guideline: There are some multi-clock design verification suites that benefit from using multiple nonblocking assignments with RHS delays; however, this coding style can be confusing, therefore placing delays on the RHS of nonblocking assignments in testbenches is not generally recommended.

Modeling Guideline:
Use continuous assignments with delays to model simple combinational logic. This coding style will accurately model combinational logic with inertial delays.Use always blocks with no delays to model complex combinational logic that are more easily rendered using Verilog behavioral constructs such as "case-casez-casex", "if-else", etc. The outputs from the no-delay always blocks can be driven into continuous assignments to apply behavioral delays to the models. This coding style will accurately model complex combinational logic with inertial delays.
Testbench Guideline: Continuous assignments can be used anywhere in a testbench to drive stimulus values onto input ports and bi-directional ports of instantiated models.

Conclusions:
Any delay added to statements inside of an block does not accurately model the behavior hardware and should not be done. The one exception carefully add delays to the right hand side of nonblocking assignments, which will accurately model transport delays, generally at the cost of simulator performance.

Adding delays to any sequence of continuous assignments, or modeling complex logic with no inside of an always block and driving the always outputs through continuous assignments with delays, accurately model inertial delays and are recommended coding styles for modeling combinational logic.

Communicating in an effective way


With this article i would like to support you in your daily communication challenges.
You will read some interesting words about how your attitude affects your communication, about how important it is to listen actively as well as to thrive on feedback.
Some aspects might be known to you, some information might be new.

Step 1: Communication usually begins with ATTITUDE...
Your attitude affects everything about your communications effectiveness.
Set your COMMUNICATIONS COMPASS on these four ATTITUDES:

  1. Service
  2. We're all in the same boat
  3. We're reasonable people, seeking reasonable solutions to complex problems
  4. Empathy
Think of a work experience in which money and time were lost because of poor communication. The single most important variable in employee productivity and loyalty turns out to be not pay, benefits or workplace environment. Rather, according to the Gallup Organization, it's the quality of the relationship between employees and their direct supervisors. One major lever here is communication!

"Communication makes or breaks that relationship!"

Step2: ...and continues with ACTIVE LISTENING...

One of the most important communication skills for today's leaders is listening. Employees, customers, suppliers: People – want to be listened to. They want leaders to take the time to ask for, listen to and consider their views and ideas.

To be an active listener, you must start with an attitude of respect for another's views, no matter how different they are from yours. By actively listening, you establish a climate free of being critical, judgmental or moralizing.

Here are some Listening Tips:

  • Visibly show that you acknowledge what the other person is saying. Eye contact, leaning forward, nods of the head, and responses such as, "I see", signal interest.
  • Understand intent by clarifying with questions. Seek further information to help you truly understand the person's feelings and views. It's important to be able to separate fact from opinion and emotions.
  • Summarize the key message that you heard by saying "You seem to be saying…" or "If I understand you correctly, you believe that…".
  • Listen between the lines to the unspoken message. Be attentive to the feelings behind the words and note any non-verbal cues.
  • Stay focused with your eyes, ears and mind. Shut out distracting background noises or actions.
And here are some Listening Tips:

  • Don't generalize with statements like, "everybody feels that way." Overstatements direct the focus away from the other person.
  • Don't advance forward by jumping to conclusions or completing the other person's comments.
  • Don't blurt out your opinion with comments like, "That's really stupid" or "That's not true".
  • Switch off your personal bias which can selectively filter or impair your ability to really listen.
  • Don't explain or interpret the other person's behavior.
  • Don't overload with "why" questions. They can create defensiveness.
  • Don't immediately counter with your own experience or solution. "Been there-done that" readily shuts down the discussion.
Questions for self assessment

To check how well you're really listening please check how you would answer the following questions to yourself. Don't cheat!
Do you listen attentively even if you don't like the person?
Is your listening uninfluenced by the sender's gender?
Do you often look at the sender?
Do you get distracted by other noises (beepers, phones…)?
Do you stop or put away what you have been working on when listening?
Do you smile, nod your head, to indicate that you are listening?
Do you look for the meaning behind the words you hear?
Are you able to withhold the judgment until the sender is finished?
Do you ask the sender to clarify the meaning of certain words?
Do you enjoy listening to others talk?

Step 3. ...as well as with THRIVING ON FEEDBACK!
You can't get real feedback without really listening!
Managing the flow of information upward is particularly difficult if the boss does not like to hear about problems. Although many people would deny it, bosses often give off signals they want to hear only good news.

  • This is the way how you can stimulate feedback:
  • Circumscribe, recapitulate with own words: "So, it is important for you that…"
  • Summarize, shorten: "Summarizing your statement, you said that…"
  • Clear up, concentrate: "The core of your statement is…"
  • Relate, arrange into a scheme: "On the one hand you see the possibility…, on the other hand…"
  • Ask, establish understanding: "What do you mean by that?"
  • Carry on, food for thought: "What would happen if…"
  • Customize, make means aware: "Whereby do you know that the problem is solved?"
And this is the way how you can stifle feedback:

  • Command, rule and request: "You have to do it!"
  • Warn, admonish, threat: "I warn you, if you do so…"
  • Moralize, preach, conjure: "I bet you insistently to do this."
  • Coach, make suggestions, give solutions: "There is only one possible solution."
  • Hold lectures, quote reasons: "The facts speak a clear language."
  • Judge, criticize, contradict: "You can't see it this way."
  • Excessive praise, flatter: "You are an intelligent human being."
  • Insult, ridicule, embarrass: "You can't couch one clear thought."
  • Interpret, diagnose: "You have problems with your authority."
  • Research, interrogate: "Why have you done that?"
  • Distract, draw aside, tease: "You've got problems."
After reading this article about "Communicating in an effective way", i hope we were able to provide you with some support for your daily communication challenges.


New Year's Wishes


  • May you get a clean bill of health from your dentist, your cardiologist, your gastro-enterologist, your urologist, your proctologist, your podiatrist, your psychiatrist, your plumber and the I.R.S/Income Tax dept.
  • May your hair, your teeth, your face-lift, your abs and your stocks not fall; and may your blood pressure, your triglycerides, your cholesterol, your white blood count and your mortgage interest not rise.
  • May New Year's Eve find you seated around the table, together with your beloved family and cherished friends.
  • May you find the food better, the environment quieter, the cost much cheaper, and the pleasure much more fulfilling than anything else you might ordinarily do that night.
  • May what you see in the mirror delight you, and what others see in you delight them.
  • May someone love you enough to forgive your faults, be blind to your blemishes, and tell the world about your virtues.
  • May the telemarketers wait to make their sales calls until you finish dinner, may the commercials on TV not be louder than the program you have been watching, and may your check book and your budget balance - and include generous amounts for charity.
  • May you remember to say "I love you" at least once a day to your spouse, your child, your parent, your siblings; but not to your secretary, your nurse, your masseuse, your hairdresser or your tennis instructor.
  • And may we live in a world at peace and with the awareness of God's love in every sunset, every flower's unfolding petals, every baby's smile, every lover's kiss, and every wonderful, astonishing, miraculous beat of our heart.

Have a wonderful New Year Ahead :-)

Future Trends!!


How long do you think DVDs have around? 20 years? 10 years? Actually, they have only been around for about seven years, but it seems like they have been around much longer. Many of us can remember life before DVDs with VCDs and though they still exist their popularity has reduced drastically. That can be attributed to how rapidly we can become acclimated to some innovations in electronics technology. I believe there are other electronics technologies, either just getting ready to take off, not widely available yet, or just around the corner, that are going to become adopted just as quickly in the near future.

While we're in the age of Ultra High speed broadband internet services, several technologies just around the corner are going to make them much faster than they are today. The typical download speeds for broadband ranges from 1.5 to 10 megabits per second (mbps) today. Within the next year, speeds of 15-20 mbps will be available to the average consumer. Then, shortly thereafter, speeds of up to 25, 50, 75, and even 100 mbps will be available in some places. In the not-so-distant future, speeds of 25-100 mbps is will be quite common. "Fast TCP", which is currently being tested, has the potential to turbo-charge all forms of currently available broadband internet connections without requiring any infrastructure upgrades. It will better utilize the way in which data is broken down and put back together within traditional internet protocols.

All the major phone companies are currently in the process of replacing their copper wires with high capacity fiber optic lines. Fiber optic lines will greatly increase the amount of bandwidth that can be delivered. Fiber optics will allow phone companies to deliver video, either via a cable TV-type platform or a TV over Internet Protocol (TVIP) platform (see my October 7 column), and faster DSL speeds. The current breakthrough is Triple play by which you have TV, Internet and Phone on the same medium, you can get more info on this by googling around. Eventually, the current internet as we know it will be scrapped and completely replaced with a whole new internet called "Internet 2." This new internet is expected to provide speeds of up to 6000 times faster than current broadband connections!

Another technology item that you've probably heard a lot about recently is digital television. Digital TV uses a different wavelength than traditional analog TV and has a much wider bandwidth. It also has a picture that never gets "snowy" or "fuzzy." If the signal is not strong enough, you get no picture at all, rather than the fuzzy picture you sometimes get with analog. In order to receive digital signals over the airwaves, you must have a digital TV set (one with a digital tuner inside) or an analog TV with a set-top converter. Cable and satellite TV also use digital formats, but unlike broadcaster signals, their non-High Definition digital signals are automatically converted to a format an analog TV can process, so a digital TV or converter is not needed. High Definition Television formats, even on cable to satellite, require a digital TV or a converter (more on High Definition later).

All broadcasters are now doing some broadcasts on their digital channels in addition to their normal broadcasts on their analog channels, but they were originally supposed to completely convert over from analog signals to digital signals by the end of 2006. However, there is an exception that allows them to wait until 85% of the television sets in their market are digital. This could take 10 years or more to happen. Congress and the FCC are now looking at imposing a hard deadline on all broadcasters to convert to digital signals by 2009. Once they all convert to digital signals, their analog channels will taken back by the FCC and used for other purposes like emergency signals.

High Definition Television (HDTV) is one possible use of digital signals. HDTV uses the entire digital bandwidth and is the crystal clear format you've probably seen on TVs in electronics stores. It has no visible lines on the screen. Someone once described it as being like "watching a movie in the theater." Keep in mind that all HDTV is digital, but not all digital is HDTV. Along those same lines, not all digital TVs are HDTVs. Since digital TVs are very expensive and those with HDTV capability are even more expensive, consumers really need to keep this in mind.
The other possible use of digital signals is channel compression, often referred to as "multicasting." Non-HDTV programming does not utilize the entire width of a digital signal. Therefore, it is possible to compress two or more channels of programming into one digital signal. Satellite and cable operators do this all the time with their non-HDTV digital channels, but this process is transparent so many people don't realize it. Many broadcasters plan to use their digital signals this way during times when they are not being used for HDTV programming. For example, some plan to air all news and all weather channels in addition to their regular channels of programming.

TV recording and playback technology is changing as well. DVD recorders, which debuted about four years ago, have now become affordable to the average family. A couple of years ago, they were priced above $1000, but now you can get them for around $25, in many cases. The main sticking point now with DVD recorders is that not all of them will record/play all three of the competing formats: DVD-RAM, DVD-RW, DVD+RW. They will have difficulty gaining wide acceptance from the public until one format is settled on or all recorders can record and play all three formats. Also now we have HD DVD and Blu Ray which boast of enormous storage capabilities.

One the other hand, digital video recorders (DVRs) and personal video recorders (PVRs), just two names for something that is really the same thing, seem to be gaining quickly in popularity. DVRs/PVRs utilize a hard drive to record programs, without the need for discs or tapes. DVRs/PVRs with larger hard drives are becoming available and less expensive all the time. These devices can record one show while you are watching another. They can record more than one show at a time. They allow you to watch the part of a show that has already been recorded while the remainder of that show is still being recorded. They allow for easy scanning, searching, and skipping through recorded programs and even allow you to skip commercials with one touch of a button. They allow you to pause live programs while you answer the door or go to the restroom and then pick up where you left off when you get back. With these devices, recording can be automatic, i.e., you can program them to automatically record every episode of your favorite shows, no matter when they air. You can also have them automatically find and record programs that match your interests. In addition, video can be automatically downloaded to the device via a phone connection. TiVo, the leading brand in the industry, has announced that it will be teaming up with Netflix next year to allow downloading of movies on demand via a broadband internet connection (see my October 7 column for more details).

DVRs/PVRs are becoming so popular that cable and satellite TV providers have begun including them as add-ons to their receivers, either at no extra cost or for a small additional monthly fee. About the only shortcoming of DVRs/PVRs is the fact that they can't play pre-recorded DVDs or tapes, so you would still need your DVD player or VCR if you rent or purchase movies. However, hybrid devices which combine DVRs/PVRs with a DVD player/recorder and/or VCR are now hitting the market. Those devices would not only get rid of that problem but would also give you the option of permanently transferring a recorded show/movie from a hard drive to a recordable DVD.

Flat screen and flat panel TV technology is also starting to boom. Many people are confused about the difference between flat screen TVs and flat panel TVs. Flat screen TVs use the old cathode ray tube (CRT) technology for their picture tubes and are therefore bulky like traditional TV sets. However, they are different from traditional TV sets in that they have a flat screen. They deliver a picture that doesn't have as much glare as traditional, more round screens. Also, the picture will look the same to everyone in the room, no matter where they are sitting. The picture on a traditional screen looks distorted when viewing it from an angle.
Flat panel TVs, on the other hand, utilize either liquid crystal display (LCD) or plasma technology instead of the old CRT technology and are generally just a few inches thick. Many of them can be hung on a wall. In fact, flat panel TVs that are flatter than a credit card will be coming soon! What's the difference between LCD and plasma? LCD is generally used for flat panel TVs with a display of less than 30 inches and usually has a brighter picture and better contrast than plasma. LCD is used for flat panel computer monitors as well. Plasma is generally used for flat panel TVs with a display of more than 30 inches and has a better color range than LCD. Plasma is becoming more common as TVs get bigger and flatter.

Although I'm not so sure about this one, I will include "entertainment PCs" because of their tremendous potential to revolutionize home entertainment. The concept of "entertainment PCs" is being hailed right now by both Microsoft and Intel. In fact, Microsoft has developed a special operating system for them. They could be used as the hub for all home entertainment and could enhance a family's experience of television, radio/music, and internet and actually help to combine all of these into one. They could be used to download content from the internet and play it on a TV. They could provide such sophisticated TV recording interfaces that VCRs, DVDs, and DVRs/PVRs could all eventually become obsolete. In addition, they could be a better source for photograph and home video editing and processing than regular PCs. With that being said, I'm not so sure that people will be willing to accept PCs as a source of home entertainment. Bill Gates begs to differ and is willing to put his money where his mouth is.

Obviously, not all of the cutting edge electronics technologies mentioned above will meet with great success. Some of them might actually go the way of Betamax, digital audio tape (DAT), and DIVX. However, many of them are sure to catch fire and become such an intricate part of our everyday lives that we'll wonder how we ever got along without them. Which ones will they be? Only time will tell.

Gate Level Simulation, Part - II


Gate level simulation is used in the late design phase to increase the level of confidence about a design implementation and to complement verification results created by static methods (formal verification and static timing analysis). In addition to the disadvantages of medium to long run times to simulate comprehensive vector sets on large designs, the coverage of potential functional and timing problems highly depends on the quality of the input stimulus and cannot be guaranteed in a practical way. In some cases, however, a gate level simulation can help to verify dynamic circuit behavior that cannot be accurately verified with static methods. For e.g. the start up and reset phase of a chip. To reduce the overall cycle time, only a minimum amount of vectors should be simulated using the most accurate timing model available (parasitics extracted from post-layout database).

Unit Delay Simulation:
The netlist after synthesis, but before routing does not yet contain the clock tree. It does not make sense to use SDF backannotation at this step, but gatelevel simulation may be used to verify the reset circuit, the scan chain or to get data for power estimation. If no backannotation is used, simulators should use Libraries which have the specified block containing timing args disabled and using distributed delays instead. The default delay for a storage element at 10 ps, for a combinatorial gate 1 ps and a clock gating cell 0 is the most secure possibility to run unit delay simulation, and process size and performance are optimized if the specify block is disabled.

Full Timing Simulation (With SDF):
Simulation is run by taking full timing delays from sdf. The SDF file is used to back annotate values for propagation delays and timing checks to the Ver-ilog gate level netlist.

Comments are greatly appreciated.

Glossary of EDA Terms


Verilog rules that can save your breath !


This article contains some thoughts of mine about how and engineer should write Verilog code for Synthesis, general rules that will save you headaches if you follow, and how a Verilog file should be layed out.
Rules:
  • If you don't know what hardware the code you just wrote is, neither will the synthesizer.
  • Remember that Verilog is a Hardware Description Language (HDL) and as such it describes hardware not magical circuits that you can never actually build.
  • You should be able to draw a schematic for everything that you can write Verilog for.
  • Be sure to know what part of your circuit is combinational and which parts are sequential elements. If you do not know or the code is written to be too hard to figure this out, the synthesizer will probably not be able to figure it out either. I recomend making the combinational logic very separate from sequential logic. This prevents errors later. It also prevents level high latches from being synthesized where you meant to have flip-flops. I also recomend having a naming convention such that you can tell what is a state holding element at all times. I use "_f" post-pended to all registers that are flip-flops.
  • I recomend having a style for your inputs and outputs. I list them in the following order: outputs, inouts, special inputs such as clk and reset, inputs.
  • When instantiating a module, always put the names of the signals that you are conecting to inside of the module with the notations where you have period, module signal name, thing you are connecting. This prevents errors when you change underlying modules or someone resorts the parameters.
  • Unlike a language like C which is rather strongly typed, in Verilog, which is also strongly typed, everyting is of the same type and it is easy to reorder parameters and not get errors becasue everything is just a wire.
  • Example of wrong module instantiation: nand2 my_nand(C, A, B);
  • Example of correct module intantiation: nand2 my_nand(.out(C), .in1(A), .in2(B));
  • Make your circuit synchronous whenever possible. Synchronous design is much easier than asynchronous.
  • Also reduce the number of clock domains and clock boundaries whenever possible.
  • Also remember that crossing clock domains in FPGAs is difficult because LUT's glitch in different ways than normal circuits. This causes problems with asynchronous circuits.

Verilog files should be laid out like this..

  • define consts
  • declare outputs (these are _out)
  • declare inouts if any (these are _inout)
  • declare special inputs such as clk and reset
  • declare inputs (these are _in)
  • declare _all_ state (these are _f)
  • declare inputs to state with (these have same name as state but are _temp)
  • declare wires (naming not restricted except connections of two instantiated modules are usually of the form A_to_B_connection)
  • declare 'wire regs' (naming not restricted except connections are usually of the form A_to_B_connection and variables that are going to be outputs, but still need to be read and you don't want inouts get _internal postpended)
  • do assigns
  • do assigns to outputs
  • instantiations of other modules
  • combinational logic always @'s are next
    do the always @ (posedge clk ...) and put reset values here and assign _temps to _f's (ie state <= next_state). I personally think that there should be no conbinational logic inside of always @(posedge clk's) with the exception of conditional assignment (write enables) becasue all Verilog synthesizers understand write enables on flip-flops.

VHDL Online


http://esd.cs.ucr.edu/labs/tutorial/VHDL_Page.html

  • Books
  • Tutorials
  • Examples
  • Tools
  • Download
  • Others

VHDL Tutorial: Learn by Example

  • Basic Logic Gates
  • Combinational Logic Design
  • Typical Combinatinal Logic Components
    Latch and Flip-Flops
  • Sequential Logic Design
  • Typical Sequential Logic Components
http://esd.cs.ucr.edu/labs/tutorial/

Embedded System Design: A Unified Hardware/Software Introduction


Some web resources, references, labs, and slides.
http://esd.cs.ucr.edu/

VLSI Training Institutes


Updated 15 Jan 2011, by Guest Blogger:
Since this article was last published in Nov, 2006 lot of development has happened in the VLSI training space. To understand what is more suited for you and to select the right institution please read further at Career Counseling.
--
Responding to request from a reader "Venkat" regarding VLSI training institutes..

The first question i would ask anyone who is looking forward to joining a VLSI training institute is what exactly they are looking for? I will give links to some article where you can decide, later in the article.

I feel that many institutes teach just bare basics (which you can find on the blogs and websites around the net, or rather your 4 years of Engineering/BE/BS) after gulping huge lumpsums of $$. How many of these institutes target real problems? Or rather which will be helpful when you enter the industry and can say that i targeted so and so problem and solved it the so and so way. Wouldn't that be great. Atleast that you can say as experience.

Some teach assembly programming, verilog, VHDL etc. Which is ok, but can also be done by self learning with little effort. Why spoon feeding?

My answer to this query would be just plain "Dont go anywhere near them!" They are not worth it. Seriously !!

But if you still think that you need to throw away your money... then follow these links below..
http://www.angelfire.com/electronic/in/vlsi/training.html
http://in.geocities.com/srinivasan_v2001/technical/vlsi_training.html
http://www.asic-world.com/verilog/verifaq4.html

Synthesis


Logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level (RTL) or behavioral is turned into a design implementation in terms of logic gates. Some tools can generate bitstreams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs. Logic synthesis is one aspect of electronic design automation.

History of Logic Synthesis
The roots of logic synthesis can be traced to the treatment of logic by George Boole (1815 to 1864), in what is now termed Boolean algebra. In 1938, Claude Shannon showed that the two-valued Boolean algebra can describe the operation of switching circuits. In the early days, logic design involved manipulating the truth table representations as Karnaugh maps. The Karnaugh map-based minimization of logic is guided by a set of rules on how entries in the maps can be combined. A human designer can only work with Karnaugh maps containing four to six variables.

The first step toward automation of logic minimization was the introduction of the Quine-McCluskey algorithm that could be implemented on a computer. This exact minimization technique presented the notion of prime implicants and minimum cost covers that would become the cornerstone of two-level minimization. Another area of early research was in state minimization and encoding of finite state machines (FSMs), a task that was the bane of designers. The applications for logic synthesis lay primarily in digital computer design. Hence, IBM and Bell Labs played a pivotal role in the early automation of logic synthesis. The evolution from discrete logic components to programmable logic arrays (PLAs) hastened the need for efficient two-level minimization, since minimizing terms in a two-level representation reduces the area in a PLA.

However, two-level logic circuits are of limited importance in a very-large-scale integration (VLSI) design; most designs use multiple levels of logic. An early system that was used to design multilevel circuits was LSS from IBM. It used local transformations to simplify logic. Work on LSS and the Yorktown Silicon Compiler spurred rapid research progress in logic synthesis in the 1980s. Several universities contributed by making their research available to the public; most notably, MIS [13] from University of California, Berkeley and BOLD from University of Colorado, Boulder. Within a decade, the technology migrated to commercial logic synthesis products offered by electronic design automation companies.

Behavioral synthesis
With the goal of increasing designer productivity, there has been a significant amount of research on synthesis of circuits specified at the behavioral level using a hardware description language (HDL). The goal of behavioral synthesis is to transform a behavioral HDL specification into a register transfer level (RTL) specification, which can be used as input to a gate-level logic synthesis flow. Behavioral optimization decisions are guided by cost functions that are based on the number of hardware resources and states required. These cost functions provide a coarse estimate of the combinational and sequential circuitry required to implement the design.

The tasks of scheduling, resource allocation, and sharing generate the FSM and the datapath of the RTL description of the design. Scheduling assigns operations to points in time, while allocation assigns each operation or variable to a hardware resource. Given a schedule, the allocation operation optimizes the amount of hardware required to implement the design.

Multi Level Logic Minimization
Typical practical implementations of a logic function utilize a multilevel network of logic elements. Starting from an RTL description of a design, the synthesis tool constructs a corresponding multilevel Boolean network.

Next, this network is optimized using several technology-independent techniques before technology-dependent optimizations are performed. The typical cost function during technology-independent optimizations is total literal count of the factored representation of the logic function (which correlates quite well with circuit area).

Finally, technology-dependent optimization transforms the technology-independent circuit into a network of gates in a given technology. The simple cost estimates are replaced by more concrete, implementation-driven estimates during and after technology mapping. Mapping is constrained by factors such as the available gates (logic functions) in the technology library, the drive sizes for each gate, and the delay, power, and area characteristics of each gate.
[edit]

Commercial logic synthesis
Examples of software tools for logic synthesis are Design Compiler from Synopsys and the humorously named BuildGates, from Cadence Design Systems. Both of these target ASICs. Example of FPGA synthesis tools include Synplify from Synplicity, Leonardo and Precision from Mentor Graphics and BlastFPGA from Magma Design Automation.

Comprehensive Verilog Tutorials - Introduction


The history of the Verilog HDL goes back to the 1980s, when Gateway Design Automation developed Verilog-XL logic simulator, and with it a hardware description language.Cadence Design Systems acquired Gateway in 1989, and with it the rights to the language and the simulator. In 1990, Cadence put the language into the public domain, with the intention that it should become a standard, non-proprietary language.

The Verilog HDL is now maintained by a non profit making organisation, Accellera, which was formed from the merger of Open Verilog International (OVI) and VHDL International. OVI had the task of taking the language through the IEEE standardisation procedure. In December 1995 Verilog HDL became IEEE Std. 1364-1995. A revised version was published in 2001: IEEE Std. 1364-2001. This is the current version.

Accellera have also been developing a new standard, SystemVerilog, which extends Verilog. SystemVerilog is also expected to become an IEEE standard.

Comprehensive Verilog Tutorials - Welcome


This is an Introductory & Comprehensive Verilog Course, which covers..

  1. Modeling Designs for Digital Simulation.
  2. Modeling Designs for Synthesis.
  3. Design Verification using Verilog HDL.

To gain the most benefit from this course, you should:

  • Have a background in Electronics Engineering.
  • Digital Components like AND, XOR, MUX, Flip-Flop, etc.
  • Basic Computer Architectures, knowledge of ALUs, State Machines etc.

Good Luck.

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Added Features!


After much awaited delay due to developments on the blogger in beta, i m happy to announce that i have successfully converted/moved to beta.
This enables me to mainly..
  • categorize posts(labelling is needed)
  • display the latest comments on the sidebar(to be added) etc.
  • add relevant links
  • etc.
I hope you will like it new.
As you have already noticed, i have started a new series in Gate Level Simulation (GLS). This will take time and would appreciate your patience.

Gate level simulation - Introduction


With wide acceptance of STA and Formal verification tools by the industry, one question still arises in the minds of many, "Why do we need gate-level simulation?"

The common reasons quoted by many engineers are simple.
  1. To check if reset release, initialization sequence, and boot-up is proper.
  2. Since Scan insertions occur during and after synthesis, they are not checked by simulations.
  3. STA does not analyze asynchronous interfaces. This is used to validate the constraints used in STA and LEC. Static verification tools are constraint-based and they are only as good as the constraint used. Unchecked use of wildcards and late design changes not propagating to constraints or incorrect understanding of the design require validation of these constraints.
  4. Unwarranted usage of wild cards in static timing constraints set false and multi-cycle paths where they don't belong. This can also be due to design changes, misunderstanding or typos.
  5. Usage of create_clock instead of using create_generated_clock between clock domains.
  6. For switching factor to estimate power.
  7. X's in RTL sim can be pessimistic or optimistic. Any unintended dependencies on initial conditions can be found through GLS.
  8. Design changes, a wrong understanding of the design can lead to incorrect false paths or multicycle paths in the constraints.
  9. Can be used to study the activity factor for power estimation.
  10. It's an excellent feel-good quotient that the design has been implemented correctly.
Some design teams use GLS only in a zero-delay, ideal clock mode to check that the design can come out of reset cleanly or that the test structures have been inserted properly. Other teams do fully back annotated simulation as a way to check that the static timing constraints have been set up correctly.

GLS is also used to collect switching activity for power estimation and correlation, to verify the integration of digital and analog netlists, required to simulate ATPG patterns, generate ATE test vectors, validate EDA tool flow change while moving from one vendor’s sign off tool to another, validate that RTL simulations were not having any undesired force statements from the test bench and masking bugs.

In all cases, getting a gate-level simulation up and running is generally accompanied by a series of challenges so frustrating that they invoke a shower of adjectives. There are many sources of trouble in gate-level simulation. This series will look at examples of problems that can come from your library vendor, problems that come from the design, and problems that can come from synthesis. It will also look at some of the additional challenges that arise when running a gate-level simulation with back annotated SDF.

RTL considerations and Functional verification of low power designs


This article is about RTL in a Multi-Voltage environment and it's implication on verification.

In the earlier posts i discussed Multi Voltage design infrastructure. Today let's look at 'Power Gating', the most common design style to reduce Leakage Power.

Typical characteristics of this design style are:-

  1. Some of blocks in the design will be shut-down, when not functional.
  2. There will be blocks, which are always on.
  3. These blocks could be of same voltage or different voltage.
  4. The power structure to shut-down a block could be either completely external or internal. Most commonly used is internal power structure to shut-down blocks.
  5. Either VDD or Ground can be cut-off.

Consider a classical scenario, wherein implementation/verification becomes a real challenge.

"We have a chip taped-out, working fine in 65nm. We want to add more functionality to the same chip and want to accommodate the logic within the same die-area as before. To accommodate this silicon real estate requirement, we decided to move to 45nm. Since the application as well as the technology node demands extremely low leakage, we want to shut-down some blocks in the design."

Given this, it's very very challenging to accommodate Power Gating, since this chip is not architected to accommodate Power Gating

Now, given the characteristics of Power Gating Design Style, here are some facts I think, we need to consider while Micro-Architecting the design.

RTL/Micro-Architecture requirements:-

  1. Some of the blocks will be shut-down. Does your design have control logic that generates signals locally to shut-down the block ?
    • I think, if the design was architected from the beginning with power gating design style in mind, it will have a control block, which probably might make decisions on which blocks to shut-down and when and how long this has to be shut-down etc. Now the other question that comes to mind is, Is this sufficient? Do I need a separate power control block, which takes inputs from the control logic and generates the power down signals in the desired sequence ? I think it is a good practice to introduce such logic to control the complete power-down/power-on sequence.
  2. Lets look at the control signals required:
    • Control Signal for the Power Switch (Switch_enable)
    • Control Signal for the Isolation Cell Enable (Isolate_enable)
    • Control Signal for the retention flops (Save_Restore)
      • Now, I think ideally all these control signals are derivative of each other!. Its just that these signals need to be generated in the right order for the circuit to behave as desired.
      • sequence could be:
        • Inactivity generate
          1. Generate Save_Restore: This will indicate that the retention flops needs to transfer the contents from Master Latch to Slave and go into sleep mode.
          2. Generate Isolate_enable: This will enable isolation cells to be active and clamp the output to a known voltage and state.
          3. Since all the basic elements are informed of the shut-down operation, we can now generate Switch_enable, to turn off the power rails, that control specific blocks.
          4. There could be other actions such as reduce the frequency/reduce the voltage….etc as a part of this sequencing.
          5. As a part of this sequence definition, we should define the right Assertions too, so that if the right sequence is violated, this can be flagged up-front.
        • Sequence power_sequence
          1. Save_Restore && Isolate_enable && Switch_enable ==0
          2. ##1 Save_restore ==1
          3. ##1 Save_restore && Isolate_enable == 1;
          4. ##1 Save_restore && Isolate_enable && Switch_enable ==1;
        • endsequence
  3. If the above control signals exist in RTL, these are driven by power management logic but are not connected to anything!
    • Even though as said in bullet 2 these control signals are generated by Control Logic, these are not connected to anything outside this control logic. The reasons are:-
      • Power Switch that's used to cut-off power does not exist in RTL. These get added probably during Power Planning. Floor-planning/Power Planning Engineer will add these based on the specification from the Architect of the chip. Till switches are in place Switch_enable is floating.
      • In RTL there is nothing specifically done for Retention Flop, these are coded like any other register and Synthesis tool will infer them based on some commands. Save_restore end up floating.
      • Isolation cells does not exist in the RTL and hence Isolate_enable is floating.
    • Now the Question arises. How do we simulate them? We see them in order...
      1. Power Switch Behaviour
      2. Isolation Behaviour
      3. Level Shifter Behaviour
      4. Retention flop.
Remember, we don't have any representation of the above cells in the RTL. Firstly do we need to simulate the behavior of all of them? Typically in good old days, PLI's were written by verification teams to simulate all of them.

For example say,
Power Switch Behaviour: We can write a function/pli with following specification
$power(block_to_be_pd, type_of_pd(aon/shut-down)signal_used_for_shut_down(switch_enable), acknowledge signal(acknowledge))

Now this PLI should look at the "type_of_pd", which is either always_on or shut-down and act accordingly. In case the block under consideration is of type shut-down, then whenever it detects an activity on the "switch_enable" signal, it should corrupt all the signals of the block. Once all the signals are corrupted, it should generate an "acknowledge" signal after a user specified delta delay.

In my humble opinion, this should also include something like:
#0 $power(block1)
#20 $power(block2)

This enables us to simulate the behaviour of power sequencing. There is lot more that can be added to this PLI routine such as:
  1. Trace through the fanout of all the outputs of this block. Flag an Error if corrupted signals are propagated till the reciever.
  2. When switch_enable goes inactive, either reset all the logic in the block to "X" or to some random pattern.
  3. During power up, stagger the power up of different blocks randomly!!!
  4. Emulate Impact of IR-drop using staggering principle!
Isolation Behaviour: This is again pretty straight-forward. All we need is a PLI or a simple function in Verilog, which will be something like:

$isolate(input,early_switch_enable,output,output_sense)
If "early_switch_enable" is active, maintain the output at "output_sense(1/0)" value, irrespective of the state of input.

Retention Behaviour:
This is again pretty straight-forward from a simulation perspective. The PLI or a simple function, which will be something like:
$retain
("register_names",early_early_switch_enable,wake_up)
Whenever "early_early_switch_enable" is active, copy the contents of "register_names " onto a local shadow_register or a local memory, and whenever "wake_up" goes active, reload the "register_names" with contents of the shadow_register.

Now there are various complex flavors of all the above depending the circuit behaviour of these speciall cells. The major question to be answered is, are we looking at 2 different RTL? One for synthesis without any PLIs and one for simulation with PLIs. Can these PLIs be synthesized into H/W automatically by all the EDA tools available? Is this the right approach? Can these be solved using a different approach?

More Questions that need answers..
  1. Is a proper sequence for all the control signals defined ? Examples of this could be:
    • Switch_enable @ 5ns
    • Isolate_enable @ Switch_enable "+" 10ns
    • Save_Restore @ Isolate_enable "+" 20ns
  2. Now the block, which we are trying to shut-down needs to generate an Acknowledgment signal, indicating power-up or power-down. This signal is again a floating output not driven by any logic,but is processed by the power management logic!!!
  3. Is there a requirement, such as : Block needs to be powered-up within "n" clock cycles? What if you don't receive an Acknowledge within "n" clock cycles?
  4. If all the above are taken care of during micro-architecting, there are still few more questions that need to be answered for Logic Synthesis and Functional Simulation:
    – Is Isolation Cell/Level Shifter part of your RTL ? How are you coding this ? Are you instantiating it in the RTL?
    – Are Retention Flops part of RTL ? How are you coding this ? Are you instantiating it in RTL ?
    – How will the control signal get interpreted by the implementation tool, as they (the control signals) are floating?
    – How will Acknowledge signal get generated? Since it's required by power management logic, but is not generated by any hardware?
    – How will functionality of all these get verified, given that some of them are either floating or not generated ?
    – How will the shut-down get simulated ? Nothing special is done in RTL to simulate this behaviour.
    – How do we model Shut-Down to verify the functionality?
    – How will the retention flop behaviour get simulated ? In RTL it's coded like any other register.
    – When a block wakes up from shut-down, what should be the status of all the logic? Is random better or using "X" better ? Wouldn't "X" be very pessimistic ?
    – How to simulate the behaviour of "n" clock cycle requirement of the Acknowledge Signal from power-down block ?
    – If there are some always on logic residing in a shut-down block, how do we implement them? How do we verify them ?

Todays Low Power Techniques


Lets take a look at the various low power techniques in use today.
I would classify them into 2 categories

  • Structural Techniques
    • Voltage Islands
    • Multi-threshold devices
    • Multi-oxide devices
    • Minimize capacitance by custom design
    • Power efficient circuits
    • Parallelism in micro-architecture
  • Traditional Techniques
    • Clock gating
    • Power gating
    • Variable frequency
    • Variable voltage supply
    • Variable device threshold
Which one of the above techniques are aimed at reducing Dynamic Power and Leakage Power?

Dynamic Power Reduction
  • Clock Gating
  • Power efficient circuits
  • Variable frequency
  • Variable voltage supply
Leakage Power Reduction
  • Minimize usage of Low Vt Cells
  • Power Gating
  • Back Biasing
  • Reducing Dynamic Power
  • Reduce Oxide Thickness
  • Use FINFET's

Design Elements of Low Power Design


Special cells are required for implementing a Multi-Voltage design.

  1. Level Shifter
  2. Isolation Cell
  3. Enable Level Shifter
  4. Retention Flops
  5. Always ON cells
  6. Power Gating Switches/MTCMOS switch
Level Shifter: Purpose of this cell is to shift the voltage from low to high as well as high to low. Generally buffer type and Latch type level shifters are available. In general H2L LS's are very simple whereas L2H LS's are little complex and are in general larger in size(double height) and have 2 power pins. There are some placement restrictions for L2H level shifter to handle noise levels in the design. Level shifters are typically used to convert signal levels and protect against sneak leakage paths. With great care, level shifters can be avoided in some cases, but this will become less practicable on a wider scale.

Isolation Cell:
These are special cells required at the interface between blocks which are shut-down and always on. They clamp the output node to a known voltage. These cells needs to be placed in an 'always on' region only and the enable signal of the isolation cell needs to be 'always_on'. In a nut-shell, an isolation cell is necessary to isolate floating inputs.
There are 2 types of isolation cells (a) Retain "0″ (b) Retain "1″

Enable Level Shifter: This cell is a combination of a Level Shifter and a Isolation cell.

Retention Flops: These cells are special flops with multiple power supply. They are typically used as a shadow register to retain its value even if the block in which its residing is shut-down. All the paths leading to this register need to be 'always_on' and hence special care must be taken to synthesize/place/route them. In a nut-shell, "When design blocks are switched off for sleep mode, data in all flip-flops contained within the block will be lost. If the designer desires to retain state, retention flip-flops must be used".

The retention flop has the same structure as a standard master-slave flop. However, the retention flop has a balloon latch that is connected to true-Vdd. With the proper series of control signals before sleep, the data in the flop can be written into the balloon latch. Similarly, when the block comes out of sleep, the data can be written back into the flip-flop.

Always ON cells: Generally these are buffers, that remain always powered irrespective of where they are placed. They can be either special cells or regular buffers. If special cells are used, they have thier own secondary power supply and hence can be placed any where in the design. Using regular buffers as Always ON cells restricts the placement of these cells in a specific region.

In a nut-shell, "If data needs to be routed through or from sleep blocks to active blocks and If the routing distance is excessively long or the driving load is excessively large, then buffers might be needed to drive the nets. In these cases, the always-on buffers can be used."

Power Gating Switches/MTCMOS Switch: MTCMOS stands for multi-threshold CMOS, where low-Vt gates are used for speed, and high-Vt gates are used for low leakage. By using high-Vt transistors as header switches, blocks of cells can be switched off to sleep-mode, such that leakage power is greatly reduced. MTCMOS switches can be implemented in various different ways. First, they can be implemented as PMOS (header) or NMOS (footer) switches. Secondly, their granularity can be implemented on a cell-level (fine-grain) or on a block-level (coarse-grain). That is, the switches can be either built into every standard cell, or they can be used to switch off a large design block of standard cells.