FMEA
FMEA - Failure Mode and Effects Analysis - Part 1
Failure Mode and Effects Analysis (FMEA) : A procedure for analysis of potential failure modes within a system for the …
Breakthrough
Low Voltage Is Key To Energy-Efficient Chip - Part II
I have managed to gather a real doc on the recently announced low voltage chip... These are some of the important detai…
TI
Mobile TV heats up with Broadcom's 65-nm SOC
The official news is out! Broadcom has just announced a monolithic digital CMOS mobile TV receiver/demodulator, that re…
TI
TI reveals details of 45-nm process
Rumors had been rampant for the past 3 months or so that TI had stopped development on the 45 nm node and moved on to 4…
Breakthrough
Low Voltage Is Key To Energy-Efficient Chip
News in from the International Solid State Circuits Conference in San Francisco of a new energy-efficient chip designe…
DAC 2008
The Digital Electronics Blog at Design Automation Conference (DAC)
The Design Automation Conference (DAC) website has listed this Blog in the Industry Blogs Section on the home page. Th…
Good Technology Business Blogs
Sramana Mitra 's Take on Technology Business Blogs... TechCrunch : TechCrunch reports on new technology companies …
Seminars
The Future of High Performance Memory!
Rambus India Design Seminars The Future of High Performance Memory Designs 21 February 2008 | The Leela Palac…
DesignCon 2008
DesignCon 2008
Your Design Connection Awaits! DesignCon attracts engineering professionals from various levels and disciplines and r…
TAU 2008
TAU 2008
ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU Workshop) w…
DAC 2008
ACM/EDAC/IEEE Design Automation Conference 2008
The Design Automation Conference (DAC) is the premier event for the design of electronic circuits and systems, and for …
OVM Available Now!!
The OVM is now available for download from the new OVM website . The OVM is based on the IEEE 1800 SystemVerilog stand…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 7
Hints Avoid more package references than needed Keep all objects and subprograms in the nearest possible scope Keep loc…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 6
To Avoid common Warnings Store each VHDL unit into a separate file except package header and body Signal assignments fo…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 5
Critical Policies to Keep note! Balance clock to delta accuracy Pull-ups and pull-downs have to be modeled on chip leve…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 4
To Avoid common Errors A configuration declaration is needed for each architecture in the design Design-internal refere…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 3
Portability Language for modeling should be VHDL-87 VHDL-93 keywords should not be used Verilog keywords should not be…
IFIP/IEEE VLSI-SoC 2008 International Conference, 16th International Conference on Very Large Scale Integration
IFIP/IEEE VLSI-SoC 2008 International Conference 16th International Conference on Very Large Scale Integration Oct…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 2
When Compiling (VHDL): A configuration declaration is needed for each architecture in the design Design-internal refere…
VHDL Coding Guidelines
HDL Coding Guidelines - Part 1
Coding of circuit behavior and architecture is one of the most critical steps in the whole chip development project. It…