MIT 6.823 Computer System Architecture is MIT's graduate course on how processors and memory systems are built: instruction sets, pipelining, caches, virtual memory, out-of-order execution, branch prediction, multithreading, VLIW, vector machines and multiprocessors. This post lists the twenty Fall 2007 lecture notes as they were published, explains where the course lives today, and gives a short study guide to the main ideas in each lecture.
Key takeaways
- The Fall 2007 course had 20 lectures, from early computer history (L-01) to symmetric multiprocessors and memory consistency (L-20).
- The original 2007 handout links no longer open. The course page now redirects to the current offering, numbered 6.5900 [6.823].
- MIT OpenCourseWare publishes an earlier full offering of 6.823 (Fall 2005) with lecture notes.
- The lecture sequence is a good study plan for CPU architecture interviews: pipelines, caches and virtual memory first, then out-of-order and speculative execution.
Where the 6.823 lecture notes are now (note added 1 November 2026)
We checked every link in this post on 1 November 2026:
- The individual 2007 handout files (the pdf and ppt links below) return "not found". They are kept here as the original record.
- The course page csg.csail.mit.edu/6.823 now redirects to the current offering, 6.5900 [6.823] Computer System Architecture, which at the time of checking showed the Fall 2026 term with its own lecture notes, syllabus and labs. MIT renumbered many EECS subjects, and 6.823 now carries the number 6.5900.
- MIT OpenCourseWare: 6.823 Computer System Architecture, Fall 2005 is freely available and covers much the same ground as the 2007 list below.
MIT 6.823 Fall 2007 lecture list (original post)
- L-01: Computer System Architecture, pdf, ppt [09/05/07]
- 1-Intro: Introduction to Pin, pdf [09/05/07]
- L-02: Influence of Technology and Software on Instruction Sets: Up to the dawn of IBM 360, pdf, ppt [09/10/07]
- L-03: Instruction Set Evolution in the Sixties: GPR, Stack, and Load-Store Architectures, pdf, ppt [09/12/07]
- L-04: Hardwired, Non-pipelined ISA Implementation, pdf, ppt [09/17/07]
- L-05: Instruction Pipelining and Hazards, pdf, ppt [09/19/07]
- L-06: Microprogramming, pdf, ppt [09/26/07]
- L-07: Cache Organization, pdf, ppt [10/01/07]
- L-08: Memory Management: From Absolute Addresses to Demand Paging, pdf, ppt [10/03/07]
- L-09: Modern Virtual Memory Systems, pdf, ppt [10/10/07]
- L-10: Complex Pipelining, pdf, ppt [10/15/07]
- L-11: Complex Pipelining: Out of Order Execution and Register Renaming, pdf, ppt [10/17/07]
- L-12: Branch Prediction, pdf, ppt [10/22/07]
- L-13: Speculative Execution, pdf, ppt [10/24/07]
- L-14: Advanced Memory, pdf, ppt [10/29/07]
- L-15: Multithreading, pdf, ppt [10/31/07]
- L-16: VLIW/EPIC: Statically Scheduling ILP, pdf, ppt [11/05/07]
- L-17: Vector Computers, pdf, ppt [11/07/07]
- L-18: Virtual Machines and Dynamic Translation: Implementing ISA's in Software, pdf, ppt [11/14/07]
- L-19: Reliable Architecture, pdf, ppt [11/19/07]
- L-20: Symmetric Multiprocessors: Synchronization and Sequential Consistency, pdf, ppt [11/26/07]
Courtesy: MIT
What the course covers: a study guide by theme
The twenty lectures fall into six themes. The notes below summarise the core idea of each theme in our own words so that the page is useful even without the slides.
| Theme | Lectures | Core questions |
|---|---|---|
| Instruction sets and their history | L-01 to L-03 | Why did machines move from accumulator and stack designs to general-purpose registers and load-store ISAs? |
| Basic implementation | L-04 to L-06 | How is an ISA built as a single-cycle datapath, a pipeline, or a microprogrammed machine, and what hazards arise? |
| Memory hierarchy | L-07 to L-09, L-14 | How do caches, address translation, TLBs and advanced memory techniques hide memory latency? |
| Instruction-level parallelism | L-10 to L-13, L-16 | How do out-of-order issue, register renaming, branch prediction, speculation and VLIW scheduling run more instructions per cycle? |
| Other forms of parallelism | L-15, L-17, L-20 | When do multithreading, vector units and multiprocessors beat a faster single core, and what do synchronization and memory consistency require? |
| Systems topics | 1-Intro, L-18, L-19 | How do binary instrumentation (the Pin tool used in the labs), virtual machines, dynamic translation and reliability techniques fit in? |
Pipelining and hazards (L-05, L-10)
A pipeline overlaps the stages of successive instructions. Three hazards stop it from issuing one instruction per cycle: structural hazards (two instructions need the same hardware), data hazards (an instruction needs a result that is not yet written) and control hazards (the next instruction address is not yet known after a branch). Forwarding, interlocks (stalls) and branch prediction are the standard fixes.
Caches and virtual memory (L-07 to L-09)
A cache is described by its capacity, block size and associativity. Misses are usually grouped as compulsory, capacity and conflict misses. Virtual memory maps virtual pages to physical frames through page tables, and a TLB caches recent translations so that most loads and stores do not walk the page table.
Out-of-order and speculative execution (L-11 to L-13)
Register renaming removes false dependences (write-after-read and write-after-write), so instructions can run as soon as their true inputs are ready. A reorder buffer retires results in program order, which keeps exceptions precise and lets the machine discard work after a mispredicted branch.
Multiprocessors (L-20)
Once several cores share memory, the hardware must keep caches coherent and define a memory consistency model. Sequential consistency is the simplest model to reason about: the result is as if all memory operations ran in some single order that respects each core's program order.
How to use these notes for interviews
- Start with pipelining, hazards and caches. Most CPU architecture interviews begin there.
- Be ready to draw a five-stage pipeline and show where forwarding paths go.
- Practise cache arithmetic: given capacity, block size and associativity, work out the number of sets and the tag, index and offset bits.
- Explain register renaming and the reorder buffer in plain words before using the jargon.
Our top 50 CPU architecture interview questions with answers follows much the same order, and the interview question on CPU design is a good short exercise. For background on the profession, see who are the computer architects. Short definitions of out-of-order execution and cache are on The Semiconductor Hub glossary.
Frequently asked questions
Is MIT 6.823 still taught?
Yes. As of 1 November 2026 the old course address redirects to 6.5900 [6.823] Computer System Architecture, which showed a Fall 2026 term.
Where can I get the 6.823 lecture notes for free?
MIT OpenCourseWare hosts the Fall 2005 offering of 6.823 with lecture notes. The current course site also lists its own lecture notes. The 2007 files linked above no longer open.
What are the prerequisites for 6.823?
The current course page lists 6.004 (MIT's undergraduate computation structures course) or equivalent. In practice you need digital logic, basic assembly language and a simple pipelined processor.
Which textbook pairs well with 6.823?
Hennessy and Patterson's Computer Architecture: A Quantitative Approach (Morgan Kaufmann) covers the same topics in depth and is widely used alongside graduate architecture courses.
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