How to get a free link to your ASIC or VLSI Blog?

This is how you can get a free link to your blog. If you are not already a member of the ASIC/VLSI/Digital Electronics blogging community, join it now! Then write a post in your blog with at least 2 paragraphs and add an active link to this blog below (homepage or individual post page, ie., permalink). When you are done, comment in this post giving the link to the post and we will link to your blog. You can write anything. You can praise us, just describe us, or even criticise us. However, the post must be a permanent post and should make sense, and should not be deleted after you get your free credit.

It will be greatly appreciated if you can write more, especially if you find this blog helpful. I find this blog has been helpful from the comments I have received, the feeburner subscription count and the googlepage rank :-).

Note: Your blog should be a VLSI/ASIC/Digital Electronics related blog!
Anything else will be ignored.

Good luck!
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Semiconductor forecast looks grim!

According to IC insights, the maket forecast looks grim for 2008 total worldwide IC market growth, noting shrinking demand from fabless suppliers, a weak memory market, and pricing issues that continue to plague the semiconductor industry. After yesterday's failure of US$700B bailout vote in the US house, it looks even more grim to note that spending will reduce drastically against most weak currencies which includes emerging markets.

Thanks to the reign of the capitalist US market for the past 7 decades, the Technological growth and innovation Breakthroughs are more likely to be impacted further unless the emerging markets/powers pump money into their already confident markets to keep up the pace and shift the trend from US and Europe for a more robust and sustainable world economy.

[Featured Link:]
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Simple XVGA (1024x768) Controller in Verilog

module xvga(clk,hcount,vcount,hsync,vsync);
input clk; // 64.8 Mhz
output [10:0] hcount;
output [9:0] vcount;
output hsync, vsync;
output [2:0] rgb;

reg hsync,vsync,hblank,vblank,blank;
reg [10:0] hcount; // pixel number on current line
reg [9:0] vcount; // line number

wire hsyncon,hsyncoff,hreset,hblankon; // next slide for generation
wire vsyncon,vsyncoff,vreset,vblankon; // of timing signals
wire next_hb = hreset ? 0 : hblankon ? 1 : hblank; // sync & blank
wire next_vb = vreset ? 0 : vblankon ? 1 : vblank;

always @(posedge clk) begin
hcount <= hreset ? 0 : hcount + 1;
hblank <= next_hb;
hsync <= hsyncon ? 0 : hsyncoff ? 1 : hsync; // active low
vcount <= hreset ? (vreset ? 0 : vcount + 1) : vcount;
vblank <= next_vb;
vsync <= vsyncon ? 0 : vsyncoff ? 1 : vsync; // active low

// assume 65 Mhz pixel clock
// horizontal: 1344 pixels total
// display 1024 pixels per line
assign hblankon = (hcount == 1023); // turn on blanking
assign hsyncon = (hcount == 1047); // turn on sync pulse
assign hsyncoff = (hcount == 1183); // turn off sync pulse
assign hreset = (hcount == 1343); // end of line (reset counter)
// vertical: 806 lines total
// display 768 lines
assign vblankon = hreset & (vcount == 767); // turn on blanking
assign vsyncon = hreset & (vcount == 776); // turn on sync pulse
assign vsyncoff = hreset & (vcount == 782); // turn off sync pulse
assign vreset = hreset & (vcount == 805); // end of frame

// for frame
always @(posedge clk) begin
if (vblank | (hblank & ~hreset)) rgb <= 0;
rgb <= (hcount==0 | hcount==639 | vcount==0 | vcount==479) ? 7 : 0;

//for colors (see below)
always @(posedge clk) begin
if (vblank | (hblank & ~hreset)) rgb <= 0;
rgb <= hcount[8:6];

Color chart:

RGB Color

000 black
001 blue
010 green
011 cyan
100 red
101 magenta
110 yellow
111 white

Example Pixel:

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Coaching Excellence in IC Design Teams: Why Can't we get Rid of that Thorn in our Process?

Coaching Excellence in IC Design Teams: Why Can't we get Rid of that Thorn in our Process?

Commenting on this article by Jorvig...

It is really true. In the past and including the current one i work for all suffer from the same problem. Its ironic that there is no solution in sight but i am sure somebody is reading this article and kicks a thought process to even look at it unless he isn't even aware of it.

Semiconductor Industry Links - A showcase

Below are select links to semiconductor industry companies that offer various products and/or services that impacts those embarking on new semiconductor ventures.

TechSearch International:
TechSearch is recognized as a leading consultant in the field of advanced packaging technology. Besides offering several reports on advanced packaging technology and market trends, TechSearch locates and introduces companies interested in licensing a technology to other companies or acquiring a new technology.

IC Knowledge:
IC Knowledge is an information resource specializing in integrated circuit economics, process technology, and fabrication facility design. In addition to free content posted on its web site, on a paid basis IC Knowledge offers a cost model for IC products, cost modeling services, and publications covering IC economics and technology.

Technology Forecasters:
Founded in 1987, Technology Forecasters Inc. (TFI) helps meet the information needs of electronics manufacturing services (EMS) companies, their customers, and suppliers. Through primary research, in-depth reports, specialized workshops, on-demand consulting engagements, and content-rich Quarterly Forum member events, TFI has become a leading global information resource for the EMS industry.

Chipworks is an internationally recognized technical services company that analyzes the circuitry and physical composition of semiconductors and electronic systems for a wide range of applications in patent licensing support and competitive study. Since 1992, Chipworks has successfully helped leading-edge semiconductor and electronics manufacturers, as well as start up companies achieve their goals by supporting research and development efforts in strategic product development and patent portfolio management.

Semiconductor Insights:
Semiconductor Insights helps leading-edge technology companies and licensing professionals attain their product and intellectual property goals by providing in-depth technical and patent analyses of integrated circuits and structures. The company's international client base spans Fortune 500 enterprises, governments, legal firms, start-ups, and venture capitalists. Within the semiconductor industry, Semiconductor Insights has participated in virtually every major licensing campaign since the late 1980s, and counts nearly all of the top 50 companies among its clients.

Semiconductor Equipment and Materials International (SEMI):
A global trade association that represents the semiconductor and flat panel display equipment and materials industries. The primary goal of SEMI is to help its members expand their global marketing opportunities and improve access to their customers and industry, government, and civic leaders. IC Insights is a SEMI member.

Semiconductor Fabtech:
A quarterly journal covering in the latest technological developments in the semiconductor manufacturing industry on a worldwide basis.

Courtesy: IC Insights.

Invitation to Freshers!

Infineon India - Bangalore is planning for a Fresher's Event in September 08 & thereby invites CVs of friends whose association with the software industry have just begun and would like to be a part of the growing Infineon family for taking up more challenging assignments.

Please note that the below mentioned criteria need to be met for a CV to be short listed:
  1. The candidate should have 6 months to 2 yrs. of work experience on C Programming & Operating Systems (Mandatory).
  2. Qualification - BE / Batch / ME / M.Tech - Yr. 2007 or 2008 pass out with minimum 70% aggregate
  3. The Subject line of email should contain the following information in the below mentioned format: <>
  4. The File name should contain the following information in the below mentioned format: <_>
  • You will be updated on the status of your referral only when the candidate gets an offer letter from Infineon.
  • Timeline for sending CVs: September 24th, 2008 to September 26th , 2008.
  • Local candidates preferred (Outstation candidates need to bear to and fro expenses on their own).
  • Please send the CVs to: only.
  • Short listed candidates will be called for a written test on C followed by interview/s.
  • If you have referred your friends profiles for the last 6 months, please do not resend those profiles.
Thanking you for your continued patronage.

VLSI Interview Questions

One day you are strolling the hallways in search of inspiration, when you bump into a person from the marketing department. The marketing department has been out surfing the web and has noticed that companies are advertising the MIPs/mmG , MIPs/Watt, and Watts/cm_ of their products. This wide variety of different metrics has confused them.

Explain whether each metric is a reasonable metric for customers to use when choosing a system.
If the metric is reasonable, say whether "bigger is better" (e.g. 500 MIPs/mmG is better than 20 MIPs/mmG ) or "smaller is better" (e.g. 20 MIPs/mmG is better than 500 MIPs/mmG ), and which one type of product (cell phone, desktop computer, or compute server) is the metric most relevant to. (NOTE: Justify your answers :-))

MIPs/mmG reasonable? [NO]
MIPs/mmG is measuring performance per area. Although we often make performance/area tradeoffs on a particular chip, the reasons for being concerned about area are based on manufacturing cost of the chip. Area by itself, is generally not a primary concern. There is one semi-plausible argument that could be made for the reasonableness of this metric. When looking at chips for cell phones, we could trade offsmall size and area, because the size of a cell phone is an important concern for consumers.

MIPs/Watt reasonable? [YES]
This metric is measuring performance per unit of power consumption. In a market segment that is concerned about both performance and power, this metric is of direct concern.
Which is better? [bigger is better]
Increasing performance and decreasing power consumption are both good things.
Most relevant product? [cell phone]
Of the three candidate products, cell phones are most sensitive to power consumption and are most likely to use MIPs as a measure of performance. Desktop PCs and compute servers generally use SPEC benchmarks for performance metrics.

Watts/cm_ reasonable? [YES]
This metric is measuring power consumption (or heat generation) per unit of volume. When heat generation is a concern, the primary concern is how much heat is generated per volume of space. There are three broad categories: no active cooling needed, air cooled (e.g. fans), liquid cooled (e.g. liquid nitrogen).
Which is better?
[smaller is better]
The less heat that is generated per volume of space, the less need there is for active cooling, and the more comfortable the temperature is.
Most relevant product? [server]
Cell phones generally don't generate enough heat to have this metric be of concern. Desktop PCs generally are not packed into a room so tightly that the volume of the PC is of concern. Compute servers tend to be packed into a rooms and on racks as densely as possible, so their volume and heat dissipation are of concern.
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Digital Design Interview Questions

Your task is to do the power analysis for a circuit that should send out a one-clock-cycle pulse once every 16 clock cycles. (That is, the output is '0' for 15 clock cycles, then '1' for one cycle, then repeat with 15 cycles of '0' followed by a '1', etc.)

You have been asked to consider three different types of counters: a binary counter, a Gray-code counter, and a one-hot counter. (The table below shows the values from 0 to 15 for Gray-code counting). Your implementation technology is an FPGA where each CLB has a programable combinational circuit and a flip-flop. The combinational circuit has 4 inputs and 1 output.

In a CLB, the capacitive load of the combinational circuit is twice that of the flip-flop.
You may assume that all counters:
  1. are implemented on the same fabrication process
  2. run at the same clock speed
  3. have negligible leakage and short-circuit currents
What is the relative amount of power consumption for the different options?

Decimal Gray
0 0000
1 0001
2 0011
3 0010
4 0110
5 0111
6 0101
7 0100
8 1100
9 1101
10 1111
11 1110
12 1010
13 1011
14 1001
15 1000

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Interview Question

Your manager has given you the task of implementing the following pseudo code in an FPGA:

if is_odd(a + d) {
p = (a + d)*2 + ((b + c) - 1)/4;
} else {
p = (b + c)*2 + d;

  • You must use registers on all input and output ports.
  • p, a, b, c, and d are to be implemented as 8-bit signed signals.
  • A 2-input 8-bit ALU that supports both addition and subtraction takes 1clock cycle.
  • A 2-input 8-bit multiplier or divider takes 4 clock cycles.
  • A small amount of additional circuitry (e.g. a NOT gate, an AND gate, or a MUX) can be squeezed into the same clock cycle(s) as an ALU operation, multiply, or divide.
  • You can require that the environment provides the inputs in any order and that it holds the input signals at the same value for multiple clock cycles.
  1. What is the minimum number of clock cycles needed to implement the pseudocode with a circuit that has two input ports?
  2. What is the minimum number of ALUs, multipliers, and dividers needed to achieve the minimum number of clock cycles that you just calculated?
  3. What is the minimum number of datapath storage registers (8, 6, 4, and 1 bit) and clock cycles needed to implement the pseudocode if the circuit can have at most one ALU, one multiplier, and one divider?
Good luck!!

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Digital "Greatest Common Divisor (GCD)" - Euclid’s algorithm

By popular demand!
Verilog module that uses Euclid's algorithm to iteratively compute the greatest common divisor of two 16-bit unsigned integer values Ain and Bin where Ain ≥ Bin.

module gcd (clk,start,Ain,Bin,answer,done);
input clk,start;
input [15:0] Ain,Bin;

output reg [15:0] answer;

output reg done;

reg [15:0] a,b;

always @ (posedge clk)
if (start)
a <= Ain; b <= Bin; done <= 0;
else if (b == 0)
answer <= a;
done <= 1;
else if (a > b)
a <= a – b;
b <= b – a;

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Digital "Square root" Computation of a number

By Popular Demand!

module sqrt (clk,data,start,answer,done);
input clk,start;
input [7:0] data;

output [3:0] answer;
output done;

reg [3:0] answer;
reg busy;

reg [1:0] bit;

wire [3:0] trial;

assign trial = answer | (1 << bit);

always @ (posedge clk)
if (busy)
if (bit == 0) busy <= 0;
bit <= bit - 1;

if (trial*trial <= data)
answer <= trial;
else if (start)
busy <= 1;
answer <= 0;

bit <= 3;

assign done
= ~busy;

Verilog - Multiplication Gotcha, did you ever know?!

Did you know this basic gotcha of verilog :-) ?

You can use the "*" operator to multiply two numbers:
wire [9:0] a,b;
wire [19:0] result = a*b; // unsigned multiplication!

If you want Verilog to treat your operands as signed two's complement numbers, add the keyword signed to your wire or reg declaration:
wire signed [9:0] a,b;
wire signed [19:0] result = a*b; // signed multiplication!

Remember: unlike addition and subtraction, you need different circuitry if your multiplication operands are signed vs. unsigned. Same is true of the >>> (arithmetic right shift)
operator. To get signed operations all operands must be signed.

To make a signed constant: 10'sh37C
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Feynman's Unsolved Puzzle?

"In The Feynman Lectures on Computation, Richard Feynman poses an interesting little puzzle involving the synchronization of finite state machines acting as generals and soldiers. While he was able to find an answer to the problem, the minimum time solution apparently eluded him, and he ended his description of the puzzle with the following Fermat-like declaration: 'Somebody has actually found a solution with this minimum time. That is very difficult though, and you should not be so ambitious.

"Here is the full description of the problem, in Feynman's own words. Please remember that these are finite state machines, so you can't use any methods that involve counting the number of soldiers or assigning a number to each soldier.

Problem 3.4: Before turning to Turing machines, I will introduce you to a nice FSM problem that you might like to think about. It is called the 'Firing Squad' problem. We have an arbitrarily long line of identical finite state machines that I call 'soldiers'. Let us say there are N of them. At one end of the line is a 'general', another FSM. Here is what happens. The general shouts 'Fire'. The puzzle is to get all of the soldiers to fire simultaneously, in the shortest possible time, subject to the following constraints: firstly, time goes in units; secondly, the state of each FSM at time T+1 can only depend on the state of its next-door neighbors at time T; thirdly, the method you come up with must be independent of N, the number of soldiers. At the beginning, each FSM is quiescent. Then the general spits out a pulse, 'fire', and this acts as an input for the soldier immediately next to him. This soldier reacts as in some way, enters a new state, and this in turn affects the soldier next to him and so on down the line. All the soldiers interact in some way, yack yack yack, and at some point they become synchronized and spit out a pulse representing their 'firing'. (The general, incidentally, does nothing on his own initiative after starting things off.)

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Interview Question - Transformed!

This is a famous interview question just that it has got a makeover!

Construct a "divisible-by-3" FSM that accepts a binary number entered one bit at a time, most significant bit first, and indicates with a light if the number entered so far is divisible by 3.
  • Draw a state transition diagram for your FSM indicating the initial state and for which states the light should be turned on. Hint: the FSM has 3 states.
  • Construct a truth table for the FSM logic. Inputs include the state bits and the next bit of the number; outputs include the next state bits and the control for the light.
  • Draw a logic schematic for the FSM.

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Interview Question!

Hello All:
In fact it has been a long time since we had posted any sort of interview questions or puzzles and so here we are with a very practical problem.

Lets see how many of you can crack it!

I will post the solutions depending on the responses. Thanks.

The problem:
The Sheel lock Company has recently received an order from Mr. Manmohan Singh for their all-digital Perfectly Perplexing Padlock(P3). The P3 has two buttons ("0" and "1") that when pressed cause the FSM controlling the lock to advance to a new state. In addition to advancing the FSM, each button press is encoded on the B signal (B=0 for button "0", B=1 for button "1").

The padlock unlocks when the FSM sets the UNLOCK output signal to 1, which it does whenever the last N button presses correspond to the N-digit combination. Unfortunately the design notes for the P3 are incomplete. Using the specification above and clues gleaned from the partially completed diagrams below fill in the information that is missing from the state transition diagram with its accompanying truth table.

When done
  • each state in the transition diagram should be assigned a 2-bit state name S1S0 (note that in this design the state name is not derived from the combination that opens the lock),
  • the arcs leaving each state should be mutually exclusive and collectively exhaustive,
  • the value for UNLOCK should be specified for each state, and
  • the truth table should be completed.

What is the combination for the lock?

Career Guidance @ The Digital ELectronics Blog

Hello & Best wishes!

Due to overwhelming responses to this Blog and successful placement of 500+ Freshers and experienced professionals alike, after requests for Job guidance through Emails and Messages we have decided to evolve the career branch ( of The Digital Electronics Blog.

You support and patronage is highly essential and as usual this service is planned to be absolutely free with help from sponsors.

Please look out at these pages for more information....

FOr any further questions you can always email us at
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