Showing posts with label Event Driven Simulation. Show all posts
Showing posts with label Event Driven Simulation. Show all posts

Event driven simulation/simulator

A latch or flip-flop does not always respond to activity on its inputs. If an enable or clock is inactive, changes at the data inputs have no effect on the circuit. As it turns out, the amount of activity within a circuit during any given timestep is often minimal and may terminate abruptly.

Since the amount of activity in a time step is minimal, why simulate the entire circuit? Why not simulate only the elements that experience signal changes at their inputs? This strategy, employed at a global level, rather than locally, as was the case with stimulus bypass, is supported in Verilog by means of the sensitivity list. The following Verilog module describes a three-bit state machine. The line beginning with “always” is a sensitivity list. The if-else block of code is evaluated only in response to a 1 → 0 transition (negedge) of the reset input, or a 0 → 1 transition (posedge) of the clk input. Results of the evaluation depend on the current value of tag, but activity on tag, by itself, is ignored.

module reg3bit(clk, reset, tag, reg3);
input clk, reset, tag;
output reg3;
reg [2:0] reg3;

always@(posedge clk or negedge reset)
if(reset == 0)
reg3 = 3'b110;
else // rising edge on clock
3'b110: reg3 = tag ? 3'b011 : 3'b001;
3'b011: reg3 = tag ? 3'b110 : 3'b001;
3'b001: reg3 = tag ? 3'b001 : 3'b011;
default: reg3 = 3'b001;

When a signal change occurs on a primary input or the output of a circuit element, an event is said to have occurred on the net driven by that primary input or element. When an event occurs on a net, all elements driven by that net are evaluated. If an event on a device input does not cause an event to appear on the device output, then simulation is terminated along that signal path.