gates

ASIC equivalent gates for Virtex

4-input LUT 6 4-input ROM 32 3-input LUT na 16x1 RAM 64 32x1 RAM 128 16 Shift Reg LUT 64 CLB flop 8 CLB latch 5 IOB flop 8 IOB latch 5 IOB Sync latch na TBUF 3 Block RAM 16,384 BSCAN 48 Clk DLL 7,000 F5 MUX …

mux

gates from mux's

OR gate from 2:1 MUX: Assumptions: 's' is the select line for the mux. 'I0 and I1' be the input data lines of the mux. 'Z' be the ouput of the Mux. a,b inputs of the OR gate. method 1 >> Connect the input b to the select line 's' of mux. Connect input 'a' to the 'I0' line input of mux. Connect the 'I1' line input of mux to LOGIC 1(VCC). Now ur mux out 'z' will be "a or b&…