Latch vs Flip-Flop: Differences, Table, Code and Examples

A latch and a flip-flop are two basic building blocks in digital electronics used to store binary data. The main difference between them is that a latch is level-sensitive: while its enable (often a clock) is active, the output follows the input. A flip-flop is edge-sensitive: it samples the input only on a clock edge and holds the value until the next edge.

Key takeaways

• A latch is transparent while its enable is active and holds when it is inactive; a flip-flop captures data only at the clock edge.
• A common edge-triggered D flip-flop is two latches in series (master and slave) on opposite clock phases.
• Latches are smaller, faster and lower power, but they make timing analysis harder because data can pass through during the whole transparent phase.
• Most RTL and FPGA design uses D flip-flops; latches are still used on purpose in clock-gating cells, latch-based high-speed and low-power designs, and some register files.
• Unintended latches in RTL usually come from an incomplete if or case in combinational logic; check the synthesis report for inferred latches.

Latch vs flip-flop comparison table

The table below shows the principal comparisons to help understand the difference better, and then we dive into a few examples. The last column adds a practitioner's note where the short answer needs qualifying.

Aspect	Flip-flop	Latch	Practitioner note
What is the basic principle?	Edge triggered	Level triggered	Usually written as edge-sensitive vs level-sensitive.
Is it controlled by a clock signal?	Yes.	No.	A basic SR latch has no clock. A gated (D) latch has an enable, and in synchronous designs that enable is often a clock phase.
What is it designed using?	Latches along with a clock.	Logic gates.	A master-slave flip-flop is two latches clocked on opposite phases. Latches are built from cross-coupled gates or, in CMOS, transmission gates and inverters.
What is it sensitive to?	Sensitive to the applied input and the clock signal.	Sensitive to the applied input signal, only when enabled.	A flip-flop only looks at D in a small window around the clock edge (setup and hold).
Speed of operation	Slow.	Comparatively fast.	A latch has fewer stages from D to Q and allows time borrowing, so latch-based paths can run faster.
Classification	Can be classified into a synchronous or asynchronous flip-flop.	NA	This usually refers to synchronous inputs (D, J, K) versus asynchronous set and reset. Latches can be ungated (SR) or gated (enable).
Working	Works using the binary input and the clock signal.	Operates only using binary inputs.	A gated latch also uses its enable input.
Power requirement	Requires more power.	Requires comparatively less power.	A flip-flop has about twice the clocked transistors of a latch, so clock power is higher.
Analysis of circuit	Easy to perform circuit analysis.	Analysing the circuit is quite complex.	Static timing analysis handles latches, but time borrowing and transparent paths make reports harder to read.
Type of operation performed	Performs synchronous operations.	Performs asynchronous operations.	Ungated latches are asynchronous; gated latches clocked by clock phases are used in fully synchronous two-phase designs.
Robustness	Comparatively more robust.	Comparatively less robust.	Mainly because glitches on D pass through a latch while it is transparent.
Dependency of operation	The operation relies on the present and past input bits along with the past output and clock pulses.	The operation depends on the present and past input along with the past output binary values.	Both are sequential: the output depends on stored state as well as current inputs.
Usage as a register	Capable of working as a register as it contains clock signals in its input.	Cannot serve as a register as the register requires further advanced electronic circuits (EC). Time also plays an essential role here.	Correction: latches can and do form registers. Latch-based register files and pipeline registers are used in many processors and low-power designs, with careful timing.
Types	J-K, S-R, D, and T flip-flops.	J-K, S-R, D, and T latches.	Correction: practical latches are SR and D (gated) latches. A JK or T latch with both inputs active and enable held high toggles repeatedly (race-around), which is why JK and T are built as edge-triggered or master-slave flip-flops.
Area impact	Requires more area.	Requires less area.	A latch is roughly half the area of a flip-flop in a typical standard-cell library.
Uses	Constitutes the building blocks of many sequential circuits such as counters.	Can be utilized for designing sequential circuits, but not generally preferred.	Latches are preferred in clock-gating cells and some high-performance and low-power designs.
Input and output	Checks the inputs and only changes the output at times defined by any control signal like the clock signal.	Responds to the changes in inputs continuously as soon as it checks the inputs.	For a gated latch, only while the enable is active.
Synchronicity	Synchronous, works based on the clock signal.	Asynchronous, does not work based on the time signal.	See the note on type of operation above.
Is it fault tolerant?	Protected against any fault.	Responsive to any occurring faults on the enable pin.	Correction: no storage element is protected against every fault. Flip-flops ignore glitches on D outside the setup and hold window, but they can still go metastable and suffer single-event upsets. Latches are sensitive to glitches on D and on the enable while transparent.

How a latch and a flip-flop behave

Putting things differently, a latch is a circuit element that can hold a state (either 1 or 0) and remain in that state until a new input signal arrives. A flip-flop, on the other hand, is designed to change state only when a specific condition is met, namely a clock edge. In other words, a flip-flop is a synchronous device that changes state only at specific points in time, whereas a latch can change state at any time while it is enabled. Additionally, flip-flops often have specific inputs for setting and resetting the state, whereas a D latch has a single data input, plus its enable, that determines the new state.

A simple way to picture the difference: for a positive-level D latch, Q copies D for the whole time the enable is high, and freezes when the enable goes low. For a positive-edge D flip-flop, Q takes the value D had just before the rising clock edge, and ignores any changes to D for the rest of the cycle.

Clocking

Flip-flops are synchronous devices that change state only on the rising or falling edge of a clock signal, whereas latches change state in response to the input signal at any time while they are enabled (or at any time, for an ungated SR latch).

Inputs

A D flip-flop has a data input (D) and a clock input (CLK), whereas a D latch has a data input and an enable. Some flip-flops also have a reset input (R) to initialise the circuit to a known state, and set inputs or scan inputs for test.

Output

Flip-flops and latches both typically provide two complementary outputs, Q and Q-bar. The output of a transparent latch is a direct function of the input, whereas the output of a flip-flop depends on both the data input and the clock edge.

Timing

Latches are considered to be faster than flip-flops because they do not wait for a clock edge to pass data. However, the timing of a flip-flop is more predictable, since it changes state only on the rising or falling edge of a clock signal. A flip-flop must meet a setup time (D stable before the edge) and a hold time (D stable after the edge); violating them can make the output metastable. A latch has setup and hold requirements around its closing edge instead.

Usage

Latches are used in applications where the timing of the input signal is less critical or where level-sensitive storage is wanted, such as holding a value for a bus or display. Flip-flops are used in synchronous circuits where the timing of the data must be controlled, such as digital clocks, counters, state machines and pipeline registers.

Types

There are several types of flip-flops, including SR, D, T, JK and master-slave flip-flops, each with its own set of inputs and outputs and specific uses in digital circuit design. Latches, on the other hand, come in two main types: SR and D latches.

How a flip-flop is built from two latches

A common implementation of a flip-flop is a pair of latches (master-slave flop). The master latch is transparent while the clock is low and the slave while the clock is high. Just before the rising edge, the master holds the value of D; at the edge the master closes and the slave opens, passing that stored value to Q. Because the two latches are never transparent at the same time, the pair behaves as a positive-edge-triggered D flip-flop.

Latches are sometimes called "transparent latches" because they are transparent (input directly connected to output) when the clock is high, for a positive-level latch. A negative-level latch is transparent when the clock is low. The clock to a latch is often called the "enable".

For more information have a look at the picture below.

Examples in Verilog, SystemVerilog and VHDL

Here are some examples and usage of latches and flip-flops in real design, along with code snippets in SystemVerilog, VHDL and Verilog. Note (November 2026): the code below has been reviewed and a few errors in the original snippets have been corrected; each change is listed under the code.

Latch

A latch is a level-sensitive device that passes its input to its output while enabled and maintains its output state while disabled. There are two common types of latches: the SR latch and the D latch.

Example usage: a latch can be used to hold a value in a digital design. In this example, a D latch captures an input signal while the enable (here named clk) is high and holds it for a display while the enable is low.

Verilog code:

module d_latch(input d, clk, output reg q);
    always @ (d or clk) begin
        if (clk)
            q <= d;
    end
endmodule

Corrected: q is now declared output reg (it is assigned inside an always block), and d is added to the sensitivity list. With only clk in the list, the simulation would not follow changes on D while the latch is open, but synthesis would still build a latch, so simulation and hardware would disagree. always @* also works.

SystemVerilog code:

module d_latch(input logic d, clk, output logic q);
    always_latch begin
        if (clk)
            q <= d;
    end
endmodule

module display(input logic signal);
    // Display the signal
endmodule

module top(input logic input_signal, input logic clk);
    logic signal_buffer;
    d_latch latch(.d(input_signal), .clk(clk), .q(signal_buffer));
    display display(signal_buffer);
endmodule

Corrected: the original positional connection d_latch latch(signal_buffer, clk, input_signal); connected signal_buffer to D and drove the top-level input from Q. Named port connections avoid this kind of mistake. always_latch tells tools that a latch is intended, and they warn if the block does not infer one.

VHDL code:

library ieee;
use ieee.std_logic_1164.all;

entity d_latch is
    port (
        d : in std_logic;
        clk : in std_logic;
        q : out std_logic
    );
end entity;

architecture behavior of d_latch is
begin
    process (d, clk)
    begin
        if clk = '1' then
            q <= d;
        end if;
    end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity display is
    port (
        sig : in std_logic
    );
end entity;

architecture behavior of display is
begin
    -- Display the signal
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity top is
    port (
        input_signal : in std_logic;
        clk : in std_logic
    );
end entity;

architecture behavior of top is
    signal signal_buffer : std_logic;
begin
    latch : entity work.d_latch
        port map (d => input_signal, clk => clk, q => signal_buffer);
    display : entity work.display
        port map (sig => signal_buffer);
end architecture;

Corrected: the original latch used if rising_edge(clk), which describes a flip-flop, not a latch. A latch tests the level (if clk = '1') and has both d and clk in its sensitivity list. The port name signal was renamed to sig, because signal is a reserved word in VHDL, and the ieee library clauses were added.

Flip-flop

A flip-flop is an edge-triggered device that stores a value on a clock edge. The four classic types are SR, D, JK and T flip-flops; the D flip-flop is by far the most used in RTL design, and the examples below use it.

Example usage: a flip-flop can be used as a memory element in a digital design. In this example, a D flip-flop stores a 1-bit counter value (it toggles on every clock, dividing the clock by two) and outputs it to a display.

Verilog code:

module d_ff(input d, clk, reset, output reg q);
    always @ (posedge clk, negedge reset) begin
        if (!reset)
            q <= 0;
        else
            q <= d;
    end
endmodule

This is a D flip-flop with an active-low asynchronous reset.

SystemVerilog code:

module d_ff(input logic d, clk, reset, output logic q);
    always_ff @(posedge clk, negedge reset) begin
        if (!reset)
            q <= 0;
        else
            q <= d;
    end
endmodule

module display(input logic signal);
    // Display the signal
endmodule

module top(input logic clk, reset);
    logic counter;
    d_ff ff(.d(~counter), .clk(clk), .reset(reset), .q(counter));
    display display(counter);
endmodule

Corrected: the original connected counter to both D and Q, so the flip-flop simply held its reset value and never counted. Feeding back the inverted output (~counter) makes it toggle. The initialiser logic counter = 0; was removed because the variable is driven by the flip-flop output, and the reset already sets it to 0.

VHDL code:

library ieee;
use ieee.std_logic_1164.all;

entity d_ff is
    port (
        d : in std_logic;
        clk : in std_logic;
        reset : in std_logic;
        q : out std_logic
    );
end entity;

architecture behavior of d_ff is
begin
    process (clk, reset)
    begin
        if reset = '0' then
            q <= '0';
        elsif rising_edge(clk) then
            q <= d;
        end if;
    end process;
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity display is
    port (
        sig : in std_logic
    );
end entity;

architecture behavior of display is
begin
    -- Display the signal
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity top is
    port (
        clk : in std_logic;
        reset : in std_logic
    );
end entity;

architecture behavior of top is
    signal counter : std_logic;
    signal counter_next : std_logic;
begin
    counter_next <= not counter;
    ff : entity work.d_ff
        port map (d => counter_next, clk => clk, reset => reset, q => counter);
    display : entity work.display
        port map (sig => counter);
end architecture;

Corrected: if reset = '0 was missing its closing quote and then; the instance label was changed from latch to ff; the flip-flop now toggles through counter_next; and the port signal was renamed to sig.

Accidental latches in RTL code

The most common way a latch appears in a design is by accident. In a combinational block, if a signal is not assigned on every path, the language requires it to keep its old value, and synthesis builds a latch to do that.

// Infers a latch: y is not assigned when sel is 0
always @* begin
    if (sel)
        y = a;
end

// No latch: y is assigned on every path
always @* begin
    y = b;          // default assignment
    if (sel)
        y = a;
end

The same applies to a case statement without a default branch, or a VHDL combinational process that does not assign an output in every branch. Default assignments at the top of the block, complete else and default branches, and SystemVerilog always_comb (which warns on inferred latches) prevent this.

Where latches are still used on purpose

• Clock gating: a standard integrated clock-gating (ICG) cell uses a latch, transparent while the clock is low, to hold the enable stable during the high phase, so the gated clock has no glitches.
• Time borrowing: in latch-based pipelines a slow stage can borrow time from the next one while the latch is transparent, which helps high-performance processor datapaths.
• Area and power: latch arrays and latch-based register files are smaller and lower power than flip-flop arrays.
• Test: scan design and level-sensitive scan design (LSSD) need extra care with latches, which is one reason many flows prefer flip-flops.

Design guidelines: latches and flip-flops

The guidelines below are from the original post, where they appeared under the heading "Deprecated hardware". They remain good defaults for most RTL and FPGA work; the note after them explains when experienced teams deliberately break the first rule.

Latches

1. Use flops, not latches.
2. Latch-based designs are susceptible to timing problems.
3. The transparent phase of a latch can let a signal "leak" through a latch, causing the signal to affect the output one clock cycle too early.
4. It is possible for a latch-based circuit to simulate correctly but not work in real hardware, because the timing delays on the real hardware do not match those predicted in synthesis.

Flip-flops

1. Limit yourself to D-type flip-flops.
2. Some FPGA and ASIC cell libraries include only D-type flip-flops. Others, such as Altera's APEX FPGAs, can be configured as D, T, JK or SR flip-flops. Note (November 2026): APEX is a discontinued Altera (now Intel) family; current FPGA logic elements provide D-type registers, and other flip-flop types are built from them with logic.

• For every signal in your design, know whether it should be a flip-flop or combinational. Examine the synthesis log file (for example the Design Compiler shell log, dc_shell.log) to see if the flip-flops in your circuit match your expectations, and to check that you do not have any latches in your design.
• Do not assign a signal to itself (for example, a <= a; is bad). If the signal is a flop, use an enable to cause the signal to hold its value. If the signal is combinational, then assigning a signal to itself will cause combinational loops, which are very bad.

Note (November 2026): "use flops, not latches" is the right default, but latches are intended in clock-gating cells, in some high-speed latch-based designs and in latch-based memories, where the timing is closed with static timing analysis that understands time borrowing. For a balanced view, read are latches really bad for a design? on this blog.

Worked example: time borrowing in numbers

Take a 1 GHz clock (1,000 ps period, 50% duty cycle) and two logic stages in a row: stage A needs 1,100 ps and stage B needs 800 ps. For simplicity, ignore clock-to-Q, setup time and clock skew.

• With flip-flops between the stages: each stage must finish within one 1,000 ps cycle. Stage A fails by 100 ps, even though stage B has 200 ps to spare. The whole design must slow down to about 909 MHz (1,100 ps period).
• With a latch between the stages: the latch is transparent for part of the cycle, so data from stage A can arrive 100 ps after the point where a flip-flop would have closed and flow straight on into stage B. Stage A borrows 100 ps from stage B. The pair needs 1,900 ps over two cycles (2,000 ps), so the design meets 1 GHz.

The borrowed time is limited by how long the latch stays open and by its setup time before closing, and static timing analysis checks both. This is the main reason high-performance processor teams still use latch-based datapaths.

Test yourself

Question 1: latch or flip-flop output?

The clock has a 10 ns period: high from 0 to 5 ns, low from 5 to 10 ns, rising again at 10 ns. D is 0 at the start, rises at 2 ns, falls at 4 ns and rises again at 7 ns. Sketch Q for a positive-level D latch and for a positive-edge D flip-flop, both clocked by this clock, from 0 to 12 ns.

Answer: the latch is transparent from 0 to 5 ns, so its Q follows D: high from 2 to 4 ns, then low. It is closed from 5 to 10 ns and holds 0, ignoring the rise at 7 ns. At 10 ns it opens again and Q goes high. The flip-flop samples D only at the rising edges: D is 0 at 0 ns and 1 at 10 ns, so Q is 0 until 10 ns and then 1. The 2 to 4 ns pulse appears only on the latch output, which is exactly the glitch sensitivity described in the table.

Question 2: does this code infer a latch?

always @* begin
    case (sel)
        2'b00: y = a;
        2'b01: y = b;
        2'b10: y = c;
    endcase
end

Answer: yes. When sel is 2'b11, y is not assigned, so it must hold its value and a latch is inferred. Add a default branch or a default assignment before the case.

Question 3: how many latches in a flip-flop?

Answer: a master-slave D flip-flop uses two latches, transparent on opposite clock phases. That is why a flip-flop is roughly twice the area of a latch and why it never lets data pass straight through.

What interviewers are really testing

• Whether you can draw the waveform difference (as in question 1) rather than recite "level vs edge".
• Whether you know where latches come from in RTL, how to find them in the synthesis or lint report, and how to remove them.
• Whether you know latches are not simply "bad": clock-gating cells, time borrowing and latch-based memories are deliberate uses.
• Whether you can relate both elements to timing: setup and hold for flip-flops, setup to the closing edge and time borrowing for latches, and metastability for both when inputs are asynchronous.

Related reading

• Latch based interview question
• Negative setup and hold time
• Verilog blocking vs non-blocking, myths and facts
• The Semiconductor Hub glossary entries on the flip-flop and metastability

Frequently asked questions

What is the main difference between a latch and a flip-flop?

A latch is level-sensitive: its output follows its input while it is enabled. A flip-flop is edge-sensitive: it captures its input only at a clock edge and holds it for the rest of the cycle.

Is a flip-flop made of latches?

A common edge-triggered D flip-flop is made of two D latches in series, a master and a slave, enabled on opposite clock phases. Other designs, such as pulsed latches and sense-amplifier flip-flops, exist for high-speed circuits.

Which is faster, a latch or a flip-flop?

A latch is usually faster and smaller, because it has fewer stages from input to output and it allows time borrowing. A flip-flop is easier to time and verify, which is why most synchronous designs use flip-flops.

Why are latches avoided in RTL design?

Because unintended latches, inferred from incomplete if or case statements, cause timing problems, glitch sensitivity and simulation and synthesis mismatches. Intended latches, such as those in clock-gating cells, are fine when timing analysis covers them.

What causes a latch to be inferred in Verilog or VHDL?

A combinational block in which some output is not assigned on every path. Add a default assignment, complete every if with else and every case with default (or when others in VHDL), and use always_comb in SystemVerilog.