Why the layoffs if we're still profitable?

This is the most common question being asked among engineers and rather should be asking if you are not. EDN Executive Editor Ron Wilson Explores "We see giant companies like IBM and Microsoft announce great fourth-quarter and annual results, and then follow up with a layoff announcement." We see smaller companies in the fabless world staying on track on product development, successfully sampling to key customers, and ramping revenue products—doing everything right—suddenly making significant cutbacks, either laying off people or cutting back on projects that lead to layoffs elsewhere. And we see, if we look carefully, start-ups who are on track and meeting milestones just shutting their doors. What gives?" Read Ron's complete post on EDN to understand behind the scenes financial opera of a typical Industry Giant!

Semiconductor Job Outlook

With big players joining the fray in job cuts, the semiconductor job outlook looks atrociously grim. The recent figures and estimates suggest that this recession is one that was not witnessed before and here to stay. The list below gives the more recent jobcuts and updates.
If you are someone who is affected by this crazy economy, you are not alone. Everyday millions of people, not just in the semiconductor business but in all industries go to work without knowing if their job is safe.

Is there a practical solution to end this carnage quickly? I don't think so! We just have to ride it out.

Wikipedia: The Missing Manual

Wikipedia: The Missing Manual is a popular how-to book on Wikipedia that has all the information you need to get started with editing pages on Wikipedia. Wikipedia may be the biggest group writing project ever, but the one thing you won't find in the comprehensive online encyclopedia is easy-to-follow guidance on how to contribute. Wikipedia: The Missing Manual helps you avoid beginners' blunders and gets you sounding like a pro from your first edit. It also gives you advise on creating articles, and working with the Wikipedia community to review new articles, mediate disputes, and maintain the site.
The book sells for $29.99 on Amazon but the publishers have uploaded the entire book to Wikipedia website under the GNU license. You can read the book for free, even lets you copy, translate and distribute the book in any format provided the derivative work is also free.

And like all the other pages on Wikipedia, this new "Wikipedia: The Missing Manual" Wikipedia section is open for public editing.

The Seven Habits of Highly Effective People

You can Download a free copy of "The Seven Habits of Highly Effective People" audio book by going to audible.com. To avail this offer, make sure that you select "USA" as the country when creating a free audible account on the next page.

The Seven Habits of Highly Effective People has sold more than 15 million copies worldwide while the audio version was the first non-fiction audio book in U.S. publishing history to sell more than one million copies according to Wikipedia.

Upcoming Events: Automated Design of Digital Microfluidic Lab-on-Chip

An event of VLSI Society of India!
Seminar on: Automated Design of Digital Microfluidic Lab-on-Chip (Connecting Biochemistry to Information Technology and Electronic Design Automation)
Speaker: Prof. Krishnendu Chakrabarty, Dept of ECE, Duke University
Date and Venue: 11 February, 2009, 11:00AM-12:00PM, G1, TI India Campus, Bangalore
For Details click here!

Free E-Book Download - Only RSS Subscribers!

Subscribe to our RSS Feed to download your copy of the E-Book.
E-Book: The Digital Signal Processing Handbook. Read further to find out how!

To download this and future E-Book's, please look at the bottom of the post in your RSS reader. See example below!

What will be your engineering legacy?

It is no easy task to record the achievements of individual engineers nowadays. But looking at the past achievements and trends, most of them have had graduated from schools like MIT, Stanford, IITs etc. and joined a handful of companies that offered superb training grounds and career opportunities.

Checkout this article on EETimes

The Top 10 power management 'How To' design articles of 2008

EETimes has published an article on the Top 10 Power Management articles of 2008. {Follow Here}

Salary and Job Satisfaction

I picked up this survey from the web and thought should share. What do you think?[Article Here]

Advertise with us!

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Top Ten Chip Companies 2008

Based on Revenue numbers from iSuppli in $Bn.

1. Intel - 34
2. Samsung - 18
3. TI - 12
4. Toshiba - 11
5. ST - 10.7
6. Renesas - 8
7. Sony - 7
8. Qualcomm - 6.7
9. Hynix - 6.4
10. Infineon - 6.3

How to run a semiconductor company?

Anybody in this industry would agree that there are 3 things that are critical for its success.
1. Quick adaptation of Technology - Can impact chip cost, time to market and customer/market reputation! Even transfer of new technology from Engineering to production.
2. Being ahead of the competition - Bad marketing decisions and late changes in the design can adversely affect this motive. Smart decisions can avoid a critical delay. Definition of responsibilities upfront can save the project and money.
3. Making Engineers work with pride - Not just defining statement of work and schedules.Give them opportunities to interact with with other levels of management and production. Make them confident.

How many companies follow these three tenets? How many have ignored? How many have been successful? How many have failed?

Please comment with your views and experiences and lets figure of out the root cause of failure and success togather.

"Semiconductors are like a new hit song, composed on an old classical theme", writes the legendary former CEO of Toshiba Semiconductors Tsuyoshi Kawanishi in his book 'Chip Management, "What I mean by this is that the applications for semiconductors are nearly infinite, but the basic technology itself is classic".

Top 10 Ways to Save Money in a Recession

Times are tough, money's tight, and nobody should be spending more than they need. If you think you've exhausted all avenues for saving a buck, check out lifehacker's ten suggestions for saving money in a recession.

VITAL and its Origins!

Verilog started out as a proprietary simulator in 1984 and enjoyed considerable success due to its C like syntax. In 1990, Cadence Design Systems made the language public. It became an IEEE standard in 1995. VHDL was developed under contract to the U.S. Department of Defense. It became an IEEE standard in 1987. VHDL has its roots in Ada.

For many years there was intense competition between Verilog and VHDL for mind share and market share. Both languages have their strong points. In the end, most EDA companies came out with simulators that work with both. Early in the language wars it was noted that Verilog had a number of built-in, gate-level primitives. Over the years these had been optimized for performance by Cadence and later by other Verilog vendors. Verilog also had a single defined method of reading timing into a simulation from an external file. VHDL, on the other hand, was designed for a higher level of abstraction. Although it could model almost anything Verilog could, and without primitives, it allowed things to be modeled in a multitude of ways. This made performance optimization or acceleration impractical. VHDL was not successfully competing with Verilog as a sign-off ASIC language. The EDA companies backing VHDL saw they had to do something. The something was named VITAL, the VHDL Initiative toward ASIC Libraries.

The intent of VITAL was to provide a set of standard practices for modeling ASIC primitives, or macrocells, in VHDL and in the process make acceleration possible. Two VHDL packages were written: a primitives package and a timing package. The primitives package modeled all the gate-level primitives found in Verilog.

Because these primitives were now in a standard package known to the simulator writers, they could be optimized by the VHDL compilers for faster simulation. The timing package provided a standard, acceleratable set of procedures for checking timing constraints, such as setup and hold, as well as pin-to-pin propagation delays. The committee writing the VITAL packages had the wisdom to avoid reinventing the wheel. They chose the same SDF file format as Verilog for storing and annotating timing values.

SDF is the Standard Delay Format, IEEE Standard 1497. It is a textual file format for timing and delay information for digital electronic designs. It is used to convey timing and delay values into both VHDL and Verilog simulations. Another stated goal of VITAL is model maintainability. It restricts the writer to a subset of the VHDL language and demands consistent use of provided libraries. This encourages uniformity among models, making them easily readable by anyone familiar with VITAL. Readability and having the difficult code placed in a provided library greatly facilitate the maintenance of models by engineers who are not the original authors.

VITAL became IEEE Standard 1076.4 in 1995. It was reballoted in 2000. The 2000 revision offers several enhancements. These include support for multisource interconnect timing, fast path delay disable, and skew constraint timing checks. However, the most important new feature is the addition of a new package to support the modeling of static RAMs and ROMs.

Author: Keshav K, MindTree, Bangalore, India

Post a link in your comments!

I am sure you have been reading this blog and did you decide to comment? In writing your comment, you may find a need to post a reference link which may be a website or an article on the internet or just a link to your blog or website or article.

Just how easy is to do that? Well, it is simple. This is the code that you need to drop into the comment box:

Replace the URL with the URL of the site or article you are linking to and replace the Title with the title of the site or artcle.

Ps: When you place a link in the comments, it is as good as we linking to you. Now get out there and comment!!! Thats our motivation.

Thai Pongal, Makara Sankranti & Tamil New Year Greetings!

We wish all our reader a very happy Thai Pongal, Makara Sankaranti and Tamil New Tear(இனிய தமிழ் புத்தாண்டு நல்- வாழ்த்துக்கள்) 2009!

Memories - Memory Faults - Part 4

As memories grow larger, with more memory cells packed into an ever-shrinking die area, the cost to manufacture a die remains fairly constant, while the time it takes to apply test programs increases exponentially. It is estimated that the cost to test a memory chip runs from 50% to 70% of the total cost of the finished product. The first steps in reducing the cost of memory test is to understand what fault mechanisms are most likely to occur and then develop test programs that target those faults. With this approach, the manufacturer and the end-user can determine their priorities, balancing cost versus DPM (defects per million) that they can tolerate in their applications.

A number of different failure types can occur in semiconductor memories, affecting memory cell contents, cell addressing, and the time required to read out data. Some of the more common failures include the following:

Cell opens or shorts
Address non uniqueness
Cell/column/row disturb sensitivity
Sense amplifier interaction
Slow access time
Slow write recovery
Data sensitivity
Refresh sensitivity
Static data losses

Opens and shorts within semiconductor memory cells may occur because of faulty processing, including misaligned masks or imperfect metallization. These failures are characterized by a general randomness in their nature. Opens and shorts may occur at the chip connections to a printed circuit board. In a km × n memory system containing km words of n bits each, and made up of memory chips of size m × 1, a fault that occurs in bit position i of m consecutive bits is indicative of either a totally failed chip or one in which an open or short exists between the chip and the PCB on which it is mounted.

Address non-uniqueness results from address decoder failures that may either cause the same memory cell to be accessed by several different addresses or several cells may be addressed during a single access. These failures often cause some cells to be physically inaccessible. An effective test must insure that each read or write operation accesses one, and only one, memory cell.

Disturb sensitivity between adjacent cells or between cells in the same row or column can result from capacitive coupling. Slow access time can be caused by slow decoders, overloaded sense amplifiers, or an excessive capacitive charge on output circuits. Slow write recovery may indicate a saturated sense amplifier that cannot recover from a write operation in time to perform a subsequent read operation.

A memory cell can be affected by the contents of neighboring cells. Worse still, the cell may be affected only by particular combination's on neighboring cells. This problem grows more serious as the distance between neighboring cells shrinks. Refresh sensitivity in dynamic RAMs may be induced by a combination of data sensitivity and temperature or voltage fluctuations. Static RAM cells are normally able to retain their state indefinitely. However, data may become lost due to leakage current or opens in resistors or feedback paths.

By contrast, when we look at faults in random logic, that fault models other than the stuck-at model were examined. The one trait these models had in common was a susceptibility to combinatorial explosion. For very small circuits, the number of faults grew so quickly that it was simply not feasible to consider them. Memory circuits, because of their density and the close proximity of cells to one another, exhibit this problem of combinatorial explosion to a far greater degree. Hence, it becomes necessary to restrict consideration to faults that are most likely to occur.

The first step is to group the faults into three broad categories: address decoder faults, memory array faults, and read/write logic faults. From there we use the fact, that faults in memory addressing and read/write logic, which includes sense amplifiers, write drivers, and other supporting logic, can be mapped onto functionally equivalent faults in the memory array. This makes it possible to concentrate on faults in the memory array and to develop tests addressed at the functionality of the memory array.

First consider faults in the address decode logic. A fault may cause multiple cells to be accessed, or no cell may be accessed, or the wrong cell may be addressed. In the case of multiple cells being addressed, the fault may be viewed as a coupling fault between cells. If no cell is addressed, then, depending on the logic, the response from the read logic may appear as a stuck-at-1 or a stuck-at-0. If the wrong cell is addressed, then, given the presence of the opposite value in that cell, it appears as a stuck-at fault.

A fault in the read/write logic may cause an output line to be stuck-at-0 or stuckat-1. In either case, the corresponding cell may be considered to be stuck-at-0 or stuck-at-1. If there are shorts or capacitive coupling between data input or data output lines, these faults can be regarded as coupling between memory cells.

Author Disclaimer:
All the information depicted in these articles have been collated from different sources using google search and for non commercial, educational purposes only. If you think we have violated any copyright please inform us and we will correct them in our capacity, as soon as possible.

Article submitted by:
Murali of IBM

Memories - Test Patterns & Algorithms - Part 3

In this section some classical, or legacy, memory test algorithms will be examined. Memory test algorithms fall into two categories: functional and dynamic. A functional test targets defects within a memory cell, as well as failures that occur when cell contents are altered by a read or write to another cell. A dynamic test attempts to find access time failures. The All 1s or All 0s tests are examples of functional tests. These tests write 1s or 0s into all memory cells in order to detect individual cell defects including shorts and opens. However, these tests are not effective at finding other failure types.

A memory test pattern that tests for address nonuniqueness and other functional faults in memories, as well as some dynamic faults, is the GALPAT (GALloping PATtern), sometimes referred to as a ping-pong pattern. This pattern accesses each address repeatedly using, at some point, every other cell as a previous address. It starts by writing a background of zeroes into all memory cells. Then the first cell becomes the test cell. It is complemented and read alternately with every other cell in memory. Each succeeding cell then becomes the test cell in turn and the entire read process is repeated. All data are complemented and the entire test is repeated. If each read and compare is counted as one operation, then GALPAT has an execution time proportional to 4N^2, where N is the number of cells. It is effective for finding cell opens, shorts, address uniqueness faults, sense amplifier interaction, and access time problems.

Walking Pattern is similar to the GALPAT except that the test cell is read once and then all other cells are read. To create a Walking Pattern from the GALPAT program, omit the second read operation in the testbench. The Walking Pattern has an execution time proportional to 2N^2 . It checks memory for cell opens and shorts and address uniqueness.

March, like most of the algorithms, begins by writing a background of zeroes. Then it reads the data at the first location and writes a 1 to that address. It continues this read/write procedure sequentially with each address in memory. When the end of memory is reached, each cell is read and changed back to zero in reverse order. The test is then repeated using complemented data. Execution time is of order N. It can find cell opens, shorts, address uniqueness, and some cell interactions.

Galloping Diagonal is similar to GALPAT in that a 1 is moved through memory. However, it is moved diagonally, checking both row and column decoders simultaneously. It is of order 4N3 /2. Row and column GALPATs of order 4N^(3/2) also exist. Sliding Diagonal (see Figure) writes a complete diagonal of 1s against a background of 0s and then, after reading all memory cells, it shifts the diagonal horizontally. This continues until the diagonal of 1s has passed through all memory locations. The Diagonal test, of order N, will verify address uniqueness at a signifi-cant speed enhancement over the Walk or GALPAT.

Surround Read Disturb starts by creating a background of all 0s. Then, each cell in turn becomes the test cell. The test cell is complemented and the eight physically adjacent cells are repeatedly read. After a number of iterations the test cell is read to determine if it has been affected by the read of its neighbors. The operation is then repeated for a background of 1s. The intent is to find disturbances caused by adjacent cell operations. Execution time depends on the number of read cycles but is of the order N. Surround Write Disturb is identical to the Surround Read Disturb except that a write rather than a read is performed.

Write Recovery writes a background of 0s. Then the first cell is established as the test cell. A 1 is written into the second cell and the first (test) cell is read. The second cell is restored to 0 and the test cell is read again. This is repeated for the test cell and every other cell. Every cell then becomes the test cell in turn. The entire process is repeated using complemented data. This is an N^2 test that is directed at write recovery type faults. It also detects faults that are detected by GALPAT.

Address Test writes a unique value into each memory location. Typically, this could be the address of that memory cell; that is, the value n is written into memory location n. After writing all memory locations, the data are read back. The purpose of this test is to check for address uniqueness. This algorithm requires that the number of bits in each memory word equal or exceed the number of address bits.

Moving Inversions test inverts a memory filled with 0s to 1s and conversely. After initially filling the memory with 0s, a word is read. Then a single bit is changed to a 1, and the word is read again. This is repeated until all bits in the word are set to 1 and then repeated for every word in memory. The operation is then reversed, setting bits to 0 and working from high memory to low memory. For a memory with n address bits the process is repeated n times. However, on each repetition, a different bit of the address is taken as the least significant bit for incrementing through all possible addresses. An overflow generates an end around carry so all addresses are generated but the method increments through addresses by 1s, 2s, 4s, and so on. For example, on the second time through, bit 1 (when regarding bit 0 as least significant bit, LSB) is treated as the LSB so all even addresses are generated out to the end of memory. After incrementing to address 111...110, the next address generated is address 000...001, and then all consecutive odd addresses are generated out to the end of memory. The pattern of memory address generation (read the addresses vertically) for the second iteration is as follows:

0000 . . . 1111
. . .
. . .
. . .
0000 . . . 1111
0011 . . . 0011
0101 . . . 0101
0000 . . . 1111

The Moving Inversions test pattern has 12BNlog2^N patterns, where B is the number
of bits in a memory word. It detects addressing failures and cell opens and shorts. It is also effective for checking access times.

To be continued...
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Launch - I have something to explain (updated)

Hello Readers:
Today we are happy to announce the launch of our new open invitation based column called "I have something to explain". A kind of "open Mic". Here the readers of this blog are invited with a chance to write an article of their choice that is unique, original that is not already on this blog.

What you get back?
Sorry we cannot pay you monetarily but in return you will get full credit for the post, an author page with a bio and your website will also be linked at the top and bottom of every post you make. Please note we do not allow a standard author box at the end of guest posts.

When you sign up to be an author here your account is set to contributor. This basically means that your post will be published upon approval. We stress that posts will never be edited or changed in any way - if a post is not up to the quality we will not publish it. Any changes or modifications have to be done by the author.

These rules are in place to ensure that the quality of posts and integrity of the site remains high.
  • The post/article should not be reproduced anywhere else on the web including your own blog (neither party benefits from duplicate content)

  • Any images used in the post cannot mess up the design of the site. As a guideline, the max width of any picture you post should not exceed 550 pixels.

  • It is ok to link to your own blog if it is relevant to do so (eg. referring a coding example or whatnot). However, you should not write articles around topics to justify a link to your blog and you should not actively encourage visitors to visit your blog. Remember, you get a link to your blog at the top and bottom of your posts plus a link on your author page which is also linked to at the top and bottom of every post and the links are clearly marked so that your site gets exposure.

  • No affiliate codes or referral links are allowed in posts.

How do I get started?
Please contact us with some background information on yourself, your blog, your writing experience and your detailed article with images to one.nanometer@gmail.com.

You could be a full time/part time contributor to this blog!
Please contact us with information on yourself, your blog and your writing experience. We will then create your account so that you can submit a post for review. It is important that you email us afterwards telling us that you have submitted a post for review as we get a lot of submissions.

Best Regards
The Digital Electronics Blog Team

Memories - Memory Types - Part 2

Semiconductor memories are characterized according to the following properties:
Serial or random access, Volatile or nonvolatile, Static or dynamic, Destructive or nondestructive readout.

Serial access memories are those in which data are accessed in a fixed, predetermined sequence. Magnetic tape units are an example of serial access. To read a record it is necessary to read the entire tape up to the point where the desired data exists.

By way of contrast, a random access memory (RAM) permits reading of data at any specific location without first reading other data. When performing a read of a FIFO (first-in, first-out) memory, the first location stored is the first to be read out.

These memories act as buffers when transferring data between functional units with different data rates. A stack in a computer, often used to save data and return addresses, is an example of a LIFO (last-in, first-out) memory. The last data pushed onto the stack is the first data to become available when the stack contents are popped from the stack.

Memories are categorized according to whether or not they can retain information when power is removed.

A nonvolatile memory can retain information when power is removed. Examples of nonvolatile memories include magnetic cores, magnetic tapes, disks, MROMs, EPROMS, EEPROMS, and flash memories.

Volatile memory devices lose information when power is removed. Volatile memories can be further broken down into static and dynamic memories.

A static memory retains information as long as power is applied, while a dynamic memory can lose information even when power is continuously applied. Static RAMs (SRAMs) are flip-flops that, with their two stable states, can remain in a given state indefinitely, without need for refresh, as long as power is applied; that is, they are static but volatile.

The dynamic RAM (DRAM), illustrated in Figure, is an example of a dynamic memory. The cell is chosen if decoding the memory address causes its wordline to be selected. It is basically a capacitor that can either be discharged onto the bitline or that can be recharged from the bit-line. Since it is a capacitor, the charge can leak away over time. The memory system must employ refresh circuitry that periodically reads the cells and writes back a suitably amplified version of the signal. If the contents of a memory device are destroyed by a read operation, it is classified as a destructive readout (DRO); otherwise it is a nondestructive readout (NDRO) device.

DRAMs must be refreshed when their contents are read out, since a read causes the capacitor to discharge. Programmable read-only memories (PROMs) are slightly more complicated to characterize. They are static and nonvolatile. Mask programmable ROMs and fuse programmable ROMs are programmed once and thereafter can only be read.

EPROMs (erasable PROMs) can be erased by means of ultraviolet light, which involves physically removing them from the system in which they are installed. For all practical purposes, they are programmed only once because it is quite inconvenient to erase and reprogram them, unless they are being used to emulate a new design for the purposes of debugging that design.

EEPROMs (electrically erasable PROMs) can be reprogrammed after being installed in a system, but their response time is slower than DRAMs or SRAMs; hence they are confined to applications where nonvolatility is required.

Flash memories are structurally almost identical to EPROMs, but they can be reprogrammed in a system and are more dense than EEPROMs. However, EEPROMs can be programmed a bit at a time, whereas flash memories are erased a block at a time before being reprogrammed. The Venn diagram in Figure illustrates this distribution of properties among the various kinds of semiconductor memories.

To be continued...

Memories - Introduction - Part 1

Memories are pervasive in digital computing. Consider, the personal computer which has a main memory, video memory, translation ROMs, shadow ROMs, scratchpad memory, hard disk, floppy disk, CDROM, and various other kinds of storage distributed throughout. In addition, the die that contains the microprocessor also contains one or more levels of cache.

A typical PC is depicted in the block diagram below. It is basically a memory hierarchy connected by several buses and adapters and controlled by a CPU. The purpose for much of the hierarchy is to combine two or more storage systems with divergent capacities, speeds, and costs such that the combined system has almost the speed of the smaller, faster, more expensive memory at almost the cost, speed, and storage capacity of the larger, slower, less expensive memory. Clearly, not all storage devices are part of this hierarchy.

The CDROM may be used to deliver programs and/or data to an end user, and video memory is dedicated to the display console. The central processing unit (CPU) accesses many of these auxiliary memory devices through a peripheral component interconnect (PCI) bus, which regulates the flow of data through the system. Unlike the random logic that has been considered up to this point, memory storage devices are characterized by a high degree of regularity. For example, a semiconductor memory is organized as an array of cells, while storage on a hard drive is organized into cylinders. This regularity of semiconductor memories permits much greater packing of transistors on die. For example, in the PowerPC MPC750, memory accounts for 85% of the transistors but only 44% of the die area. In the Alpha 21164, 80% of the 9.6 million transistors are used for three on-chip caches, but the remaining 20% of the transistors occupy a majority of the physical die area. The various storage devices in the Figure above employ different kinds of circuits for storing and retrieving data, and different kinds of media for retaining data, hence they have unique failure mechanisms, that require different test strategies. These memories may also employ varying levels of redundancy to detect and/or correct errors during operation.

To be continued...


Got a question? Ask in the Forums

Blogger's blogging platform is great but is not powerful enough to support discussions of any kind. We had evaluated Intense Debate's web platform but observed that it lacked the handle to tweak and collect data. Keeping these factors in mind we have decided to re-open our old Google group from the attic!

So how to we plan to use this group you may ask?

Its simple. We will post all questions only to this GOOGLE GROUP. This includes interview questions. This way we can harness the power of google's flexibility and make it simple to the readers.

NOTE: Answers to all the interview questions is available only to our subscribers. Please visit the group and don't forget to give as feedback.

You could also do the following in the Groups....
1. Create custom pages.
2. Upload files.
3. Post Questions/Messages.
4. You can invite new members.
5. All messages will be moderated by us.

Featured on DFT Digest!

Though this post is late by almost 15 days i feel obligated to acknowledge the reference to a great series on "the economics of test" on this Blog.

John Ford of DFT digest has indeed appreciated much of the information shared on this series of posts while humorously pointing out the mistake in the name of the city of Nice, France :-). It was indeed a mistaken repetitive occurrence during copy paste! Thanks Bauer and John for pointing this out.

Blog Updates, Top 10 Features additions!

Hello Reader,
In this New year we are happy to announce a significantly redesigned blog which gives more flexibility and control to all. Fortunately most of the features are available only when subscribed, either by RSS or by E-MAIL.

Top 10 features:
  1. Summary of the articles on the main page! Expandable to full article when clicked on the Post Title or Link.
  2. Related posts links below the main article to access all the related articles and publications.
  3. All commenters gets the link back to his site/blog automatically. So why wait? Start commenting.....!!!!
  4. Ability to browse from Mobile phone browsers when clicked on the special link. The content is specially formatted by Google.
  5. Free SMS alerts to keep you updated anywhere anytime!
  6. Launched an updated Google group, a place for discussions and asking question and discussing daily problems in chip design.
  7. Flexibility to SOCIAL BOOKMARK to as many as 25 sites.
  8. To print all posts in a printer friendly format. Look of the "Print this post" below the expanded article.
  9. Download the PDF of the Article directly.
  10. Faster Page loading(35% faster).