Webinars
Webinar watch: Accelerating Time-To-SI-Closure
Webinar:Accelerating Time-To-SI-Closure Date:Tuesday, March 31, 2009 Time: 11 amPT / 2 pm ET Duration: 60Minutes Regist…
Showing posts from March, 2009
IEEE
Upcoming VLSI/IC Conference - Cool Chips 2009
Cool Chips 2009 IEEE Symposium on Low-Power and High Speed Chips Yokohama, Japan April 15-17, 2009 COOL Chips is an Int…
Tools
Open-Source EDA Tools - No supporters?
Why is there a lack of usable open-source tools in the commercial EDA industry? The academic world has many tools to bo…
Policies
H-1Bs: Should US visa policies adjust in this economy?
With the April 1, 2009 H-1B visa application process start date just weeks away, reports from the Valley suggest that e…
Webinars
Webinar Watch - Synopsys, A Structured Methodology for Verifying Low Power Designs
An in-depth technical webinar focusing on low power verification methodology. On Tuesday, March 31, 2009 5:00 pm, Pacif…
free
Free E-Books Download - RSS Subscribers Only!
Subscribe to our RSS Feeds to download your copy of the E-Book. E-Book: The Digital Signal Processing Handbook. Read f…
Interview Questions
Interview Question on FPGA logic synthesis
It has been a while since we posted any puzzles or interview questions to tickle everyone's teeny brains. Recession…
Events
List of VLSI & IC Conferences and Workshops
Full list of conferences, complete calendar with paper deadlines and event dates.
e-verification
e-language using Random generation approach
Specman e-language powered by random generation concept. specman e-language is an HVL (High Level Verification Language…
Verification
SOC verification
At a Glance, an ASIC (Application Specific Integrated Circuit) can consolidate the work of many chips into a single, sm…