Verilog
Verilog and Specman 'e' Interview Questions
Question 1: Write a verilog assertion for the property that vector S of length 8 is always of even parity and the Hammi…
Interview Questions
Interview Questions
Interview Questions - A startup in California
A communication device receives a clock up to X MHz. Write a verilog to verify that the clock meets this timing require…
Interview Questions
Logic Design Puzzle/Interview Question challenge
Consider the Boolean function F = ( x1 + x3 + x4 )(x2 + x3 + x4 )(x1 + x2 +x4)(x1 +x3 +x4)( x1 +x2 + x3 ). Find an…
Interview Questions
e Interview Question
Packets dispatched can be of 3 network types: atm, ieee or Ethernet. The packets have a Boolean flag field which indica…
Interview Questions
Interview Question on CPU design
A CPU has a memory unit with 32-bit instructions and a register file with 32 registers. The instruction set consists of…
Interview Questions
Interview Question
Draw the circuit diagram for barrel-shifter that can shift 3 bits in either direction. The shifter should take 3 bits a…
Interview Questions
Interview Question on FPGA logic synthesis
It has been a while since we posted any puzzles or interview questions to tickle everyone's teeny brains. Recession…
Transport Delay
Transport delay / Inertial Delay / Delta Delay
In Verilog and VHDL, there are three types of delays that are commonly used in digital logic simulation: delta delay,…
Interview Questions
Avago Technologies (former HP group) Interview Questions
How do you minimize clock skew/ balance clock tree? Given 11 minterms and asked to derive the logic function. Given C…
Interview Questions
Hynix Semiconductor Interview Questions
How do you optimize power at various stages in the physical design flow? Power optimization is an important aspect of p…
Interview Questions
Hughes Networks Interview Questions
What is setup/hold? What are setup and hold time impacts on timing? How will you fix setup and hold violations? Explai…
Qualcomm
Qualcomm Interview Questions
RTL Design In work Design Verification In work Physical Design In building the timing constraints, do you need to const…
Interview Questions
Texas Instruments (TI) Interview Questions
How are timing constraints developed? Explain timing closure flow/methodology/issues/fixes. Explain SDF (Standard Del…
Interview Questions
ST Microelectronics - Interview Questions
What were the challenges you faced in physical design, PAR (place and route), FV (Formal Verification)? What was the a…
Interview Questions
Digital design interview questions
Search in this blog for all the available articles and resources! ------------------------------- PROMOTION --------…
Interview Questions
Digital Logic Design - Interview Essentials!
Hello Readers, Due to the recent spate of Layoffs , a high amount of panic and interview preparation frenzy has seeped…
Interview Questions
VLSI Interview Questions
One day you are strolling the hallways in search of inspiration, when you bump into a person from the marketing departm…
Interview Questions
Digital Design Interview Questions
Your task is to do the power analysis for a circuit that should send out a one-clock-cycle pulse once every 16 clock cy…
Interview Questions
Interview Question
Your manager has given you the task of implementing the following pseudo code in an FPGA: if is_odd(a + d) { p = (a +…
Interview Questions
Interview Question - Transformed!
This is a famous interview question just that it has got a makeover! Question: Construct a "divisible-by-3"…