Showing posts with label Netlist. Show all posts
Showing posts with label Netlist. Show all posts

Gatevision for Netlist debugging

GateVision  is a standalone graphical netlist analyzer that allows intuitive design navigation, schematic viewing, logic cone extraction, interactive logic cone viewing, and design documentation. GateVision's easy-to-read schematics and schematic fragments provide excellent debug support and accelerate the debug process.

Key Features:

   * On-the-fly schematic creation results in very high speed and capacity
   * Automatically extracts logic cones from user-defined reference points, and shows just the important portion of the circuit
   * Interactive logic cone navigation Allows compelling signal path tracing through the complete design hierarchy
   * Search-and-show capability allows easy location of specific objects shortens debug time
   * Design hierarchy browser provides easy navigation through the design hierarchy and gives compact hierarchy overview
   * Object cross-probing highlights selected objects in all design views (schematic, logic cone and HDL view) and shortens debug time
   * Context-sensitive menus and easy-to-use GUI
   * Verilog and EDIF netlist interface allows integration s into almost any design flow
   * Userware API allows addition of custom features

Formal Verification or EquivalenceChecking

Design verification, must show that the design, expressed at the RTL or structural level, implements the operations described in the data sheet or whatever other specification exists.

Verification at the RTL level can be accomplished by means of simulation, but there is a growing tendency to supplement simulation with formal methods such as model checking. At the structural level the use of equivalence checking is becoming standard procedure. In this operation the RTL model is compared to a structural model, which may have been synthesized by software or created manually. Equivalence checking can determine if the two levels of abstraction are equivalent. If they differ, equivalence checking can identify where they differ and can also identify what logic values cause a difference in response.

Updates: 18th Dec 2008 !
Another series of steps in equivalence checking goes beyond what was described above...

RTL to Pre-Synthesis Netlist!
Pre-Synthesis Netlist Vs Post Synthesis Netlist!