Wireless
Intel Mobile Comm's is looking for a Senior Verif Engineer
This opening is in Bangalore, India and the company is looking forward to close it at the earliest Job Description: 1…
Verification
Verification
Peer code review of RTL, Test bench, Test Cases for 100% Verification closure
The topic of "peer code review" is a widely discussed topic in the context of design verification. I remember…
Verification
Acceleration And Emulation – Why HW/SW Integration Needs Both
Acceleration, Emulation, and FPGA prototypes are most talked about these days and each has a distinctive role to play.…
Verification
Cadence Debuts Verification Computing Platform
Cadence Design Systems, Inc. has announced a fully integrated high-performance verification computing platform, called …
Verification
SDRAM Memory Systems: Architecture Overview and Design Verification
DRAM (Dynamic Random Access Memory) is attractive to designers because it provides a broad range of performance and is …
Verification
Enabling Rapid, Reliable Deployment of IP into System Designs
This webcast highlights The SPIRIT Consortium's new IP-XACT 1.4 specification which expands the range of IP that c…
Verification
Boosting RTL Verification with High-Level Synthesis
Instead of prolonging the painful process of finding bugs in RTL code, the design flow needs to be geared toward creati…
Verification
Diagnosing clock domain crossing errors in FPGAs
Clock domain crossing (CDC) errors in FPGAs are elusive, and locating them often requires good detective work and smart…
Verification
The Art of Debugging: Make it Fail
"Debugging" is the most valuable engineering skills, not taught in any formal setting, and often learned the …
Verification
e Verification language is alive and well
According to Mitch Weaver, corporate vice president for front-end verification at Cadence, the e verification language…
Verification
Toyota Prius 2005: An Early Warning About Verification
In this article Richard Goering talks about a software bug in Toyota Prius 2005 and after 5 years even after a through…
Verification
Motivation: What else can we talk about verification?
Many of you already know that verification efforts are as or more important as the design efforts themselves. They cann…
Verification
Verification Sessions at DVcon 2010
Featured Tutorial: Step-By-Step Guide to Advanced Verification Tutorial!, DVcon Exhibits and Product Demos.., DVCon Pap…
Verification
Clock-Domain Crossing Verification Module
This Mentor's Verification Academy module directly addresses CDC issues by introducing a set of steps for advancing…
Verification
Questa SV/AFV: Verification Methodology Kits
Mentor Graphics provides the Methodology kit examples in open source form under the Apache-2.0 license. These kits are…
VIP
The world of HVLs and VIPs
Over the last decade functional verification of ASIC systems has witnessed a paradigm shift in verification methodologi…
Verification Plan
Verification Plan
An effective verification plan encompasses a detailed description of the complete hierachical verification methodology …
Verification
Dealing with clock jitter in DDR2/DDR3 based designs
For the past couple of days i have been part of a design that interfaces a DDR/DDR2 memory. But lately after a recent p…
Verification
SOC verification
At a Glance, an ASIC (Application Specific Integrated Circuit) can consolidate the work of many chips into a single, sm…
Verification
ASIC and FPGA Verification: A Guide to Component Modeling (Systems on Silicon)
ASIC and FPGA Verification: A Guide to Component Modeling (Systems on Silicon) by Richard Munden "As large and co…