Showing posts with label Verilog Tutorial. Show all posts
Showing posts with label Verilog Tutorial. Show all posts

Comprehensive Verilog Tutorials

The Hyper-links will be updated when the Chapter-wise Tutorials are complete!
Your comments, feedback & suggestions will be greatly appreciated.

Chapter 1: Introduction & Overview of modules and procedures
Chapter 2: Language Basics, Net & Register Data Types
Chapter 3: Verilog Simulations & Display Commands
Chapter 4: Continuous Assignments, Time Delays & Timescales
Chapter 5: Verilog Operators, Timing Controls, Decisions & Looping Statements
Chapter 6: RTL Models of Combinational Logic, Interactive Debugging
Chapter 7: RTL models of Sequential Logic, Behavioral Models of RAMs & ROMs
Chapter 8: Modeling Structural Designs
Chapter 9: Blocking & Non Blocking Assignments, State Machine Designs
Chapter 10: File I/O, Test benches, Introduction to Synthesis Design Flows
Chapter 11: Additional Behavioral Commands, Verilog Strength Handling
Chapter 12: Verilog Gate Primitives, user defined Primitives
Chapter 13: Specify Blocks, SDF Back Annotation
Chapter 14: Switch Primitives, Passive Device Modeling

Thanks to Jim Blake of Centillium, Raghav Santhanam of Synopsys & Pedro of Texas A&M University for the Tutorials and other numerous contributions.

Comprehensive Verilog Tutorials - Introduction

The history of the Verilog HDL goes back to the 1980s, when Gateway Design Automation developed Verilog-XL logic simulator, and with it a hardware description language.Cadence Design Systems acquired Gateway in 1989, and with it the rights to the language and the simulator. In 1990, Cadence put the language into the public domain, with the intention that it should become a standard, non-proprietary language.

The Verilog HDL is now maintained by a non profit making organisation, Accellera, which was formed from the merger of Open Verilog International (OVI) and VHDL International. OVI had the task of taking the language through the IEEE standardisation procedure. In December 1995 Verilog HDL became IEEE Std. 1364-1995. A revised version was published in 2001: IEEE Std. 1364-2001. This is the current version.

Accellera have also been developing a new standard, SystemVerilog, which extends Verilog. SystemVerilog is also expected to become an IEEE standard.

Comprehensive Verilog Tutorials - Welcome

This is an Introductory & Comprehensive Verilog Course, which covers..

  1. Modeling Designs for Digital Simulation.
  2. Modeling Designs for Synthesis.
  3. Design Verification using Verilog HDL.

To gain the most benefit from this course, you should:

  • Have a background in Electronics Engineering.
  • Digital Components like AND, XOR, MUX, Flip-Flop, etc.
  • Basic Computer Architectures, knowledge of ALUs, State Machines etc.

Good Luck.