VLSI design interviews mix three kinds of questions: aptitude and analytical puzzles, quick logic design brain-teasers, and deeper questions on RTL, verification, test and physical design. This page collects them in one place: the original puzzle index with links to every question tagged "Interview Questions" on this blog, a digest of eleven classic ASIC puzzles, and eight puzzles solved here step by step, with Verilog where it helps.
Key takeaways
- Most hardware puzzles test one idea at a time: a universal gate, a counting trick, a timing equation or a clock edge trick. Name the idea before you start drawing.
- Say your assumptions out loud (registered or not, reset style, which clock edge). Interviewers mark the reasoning, not only the final answer.
- Always check your answer with a small example: a truth table row, a timing number or a two-cycle waveform.
- Puzzles that produce clocks (dividers, gating) have a second question hidden inside: is the result glitch-free and safe for timing tools?
Great puzzles and VLSI design interview questions: the index
Great Puzzles / VLSI Design Interview questions
- Everything that is tagged "Interview Questions": all interview question posts on this blog
- Aptitude
- Analytical
- Quantitative
- ASIC/VLSI/SoC
- RTL/Logic Design
- Design Verification
- Design for Test
- Design for Debug
- Work in progress: questions on debug and silicon bring-up will be added here. Suggestions are welcome in the comments.
- Physical Design
Eleven classic ASIC design puzzles (external digest)
A few additional ones on asicdigitaldesign.wordpress.com, digest so far:
Note (November 2026): all eleven links above were checked and still open on the original site, which now serves them over HTTPS.
Eight puzzles solved step by step
The puzzles below are written for this page. Try each one before reading the answer.
1. Build any gate from 2:1 multiplexers
Question: Using only 2:1 muxes and the constants 0 and 1, build NOT, AND, OR and XOR.
Answer: A 2:1 mux computes y = s ? i1 : i0. Put one input on the select line and choose the data inputs:
| Gate | Select | i1 (when select = 1) | i0 (when select = 0) | Muxes |
|---|---|---|---|---|
| NOT a | a | 0 | 1 | 1 |
| a AND b | a | b | 0 | 1 |
| a OR b | a | 1 | b | 1 |
| a XOR b | a | NOT b (one more mux) | b | 2 |
Because NOT and AND can both be built, the 2:1 mux is a universal element. This is also why an FPGA lookup table, which is a tree of muxes, can implement any function.
2. XOR from NAND gates only
Question: What is the minimum number of 2-input NAND gates for a 2-input XOR?
Answer: Four. Let n1 = NAND(a, b), n2 = NAND(a, n1), n3 = NAND(b, n1), y = NAND(n2, n3). Check one row: a = 1, b = 0 gives n1 = 1, n2 = 0, n3 = 1, y = 1, which is correct for XOR.
3. Binary to Gray and back
Question: Write the conversion both ways for an N-bit value.
Answer: Binary to Gray is one XOR per bit: each Gray bit is the binary bit XOR the next higher binary bit. Gray to binary is a running XOR from the most significant bit down. Example: binary 0110 (6) gives Gray 0101; converting back, 0, 0^1 = 1, 1^0 = 1, 1^1 = 0, which is 0110 again.
module bin_gray #(parameter N = 4) (
input wire [N-1:0] bin,
output wire [N-1:0] gray,
input wire [N-1:0] gray_in,
output reg [N-1:0] bin_out
);
assign gray = bin ^ (bin >> 1);
integer i;
always @* begin
bin_out[N-1] = gray_in[N-1];
for (i = N-2; i >= 0; i = i - 1)
bin_out[i] = bin_out[i+1] ^ gray_in[i];
end
endmodule
Interview follow-up: Gray codes are used for FIFO pointers that cross clock domains because only one bit changes per increment, so a synchroniser can never capture a value that is more than one step wrong.
4. Divide a clock by 3 with a 50% duty cycle
Question: Produce a divide-by-3 clock with exactly 50% duty cycle.
Answer: A mod-3 counter alone gives a high time of one or two input periods out of three (33% or 67%). To get 1.5 periods, use both clock edges: a rising-edge flop that is high for one period, and a falling-edge copy of it that is delayed by half a period. Their OR is high for 1.5 of every 3 periods.
| Time (input periods) | 0 to 0.5 | 0.5 to 1 | 1 to 1.5 | 1.5 to 2 | 2 to 2.5 | 2.5 to 3 |
|---|---|---|---|---|---|---|
| q_pos | 1 | 1 | 0 | 0 | 0 | 0 |
| q_neg | 0 | 1 | 1 | 0 | 0 | 0 |
| clk_out | 1 | 1 | 1 | 0 | 0 | 0 |
module div3_50 (
input wire clk,
input wire rst_n,
output wire clk_out
);
reg [1:0] cnt;
reg q_pos, q_neg;
always @(posedge clk or negedge rst_n)
if (!rst_n) cnt <= 2'd0;
else if (cnt == 2'd2) cnt <= 2'd0;
else cnt <= cnt + 2'd1;
// high for one input period out of three
always @(posedge clk or negedge rst_n)
if (!rst_n) q_pos <= 1'b0;
else q_pos <= (cnt == 2'd2);
// same waveform, delayed by half a period
always @(negedge clk or negedge rst_n)
if (!rst_n) q_neg <= 1'b0;
else q_neg <= q_pos;
assign clk_out = q_pos | q_neg;
endmodule
Interview follow-up: in an ASIC, say that a derived clock built from logic must be declared to the timing tool (a generated clock), and that a duty-cycle-sensitive design needs the input clock duty cycle to be well controlled too, because the falling edge sets half a period.
5. Maximum clock frequency
Question: Clock-to-Q is 0.3 ns, the worst logic path is 2.5 ns, setup time is 0.2 ns, and the capture clock arrives 0.1 ns later than the launch clock. What is the maximum frequency?
Answer: T(min) = t(clk-q) + t(logic) + t(setup) minus skew = 0.3 + 2.5 + 0.2 minus 0.1 = 2.9 ns, so f(max) is about 345 MHz. Late capture skew helps setup but hurts hold, so the follow-up is the hold check: t(clk-q) + t(logic, min) must be at least t(hold) + 0.1 ns. The setup time and hold time explainer covers both checks in detail.
6. Is a number a power of two?
Question: Detect, in one cycle, whether an N-bit unsigned value x is a power of two.
Answer: (x != 0) && ((x & (x - 1)) == 0). Subtracting 1 clears the lowest set bit and sets the bits below it, so the AND is zero only when x had exactly one bit set. Example: x = 8 (1000), x minus 1 = 0111, AND = 0, so true; x = 6 (0110), x minus 1 = 0101, AND = 0100, so false.
7. Eight balls, one heavier, two weighings
Question: Eight identical-looking balls, one is heavier. Find it with a balance in two weighings.
Answer: Weigh 3 against 3. If they balance, the heavy ball is in the remaining 2: weigh them against each other. If one side is heavier, take its 3 balls, weigh 1 against 1; if they balance, it is the third. Each weighing has three outcomes, so two weighings separate up to 3 x 3 = 9 balls, which is the reasoning interviewers want to hear.
8. Glitch-free clock gating with a plain AND gate?
Question: Why is assign gclk = clk & en; risky when en comes from rising-edge logic, and how do you fix it?
Answer: en changes shortly after the rising edge, while clk is high, so the AND output can show a runt pulse or a clipped high phase. The standard fix is a latch that is transparent while clk is low, so en is frozen during the high phase. Library integrated clock gating (ICG) cells contain exactly this latch plus the AND gate.
module clk_gate (
input wire clk,
input wire en,
output wire gclk
);
reg en_lat;
always @*
if (!clk) en_lat = en; // transparent while clk is low
assign gclk = clk & en_lat;
endmodule
Use the library ICG cell in real designs; the model above shows the idea. For latch behaviour in general, see latch vs flip-flop: differences, table and code.
How interviewers extend these puzzles
- Change one constraint: divide by 5 instead of 3, or use only NOR gates instead of NAND.
- Ask for cost: how many gates, flops or LUTs, and what is the critical path.
- Ask for robustness: what happens after reset, during a glitch, or when a signal crosses a clock domain.
- Ask for verification: how would you prove the circuit correct in simulation, and what assertions would you write.
Mistakes to avoid
- Jumping to Verilog before you have a truth table or a waveform.
- Forgetting reset: a counter or divider with no defined start state is an incomplete answer.
- Gating or dividing clocks with logic without mentioning glitches and timing constraints.
- Answering an aptitude puzzle without explaining why the method always works.
If you are preparing for a role, the semiconductor jobs board on The Semiconductor Hub lists current openings, and the semiconductor glossary is a quick way to check terms that come up in interviews.
Frequently asked questions
What kind of puzzles are asked in VLSI interviews?
Typical ones are logic puzzles (universal gates, Gray code, counters, clock dividers), timing puzzles (maximum frequency, setup and hold with skew) and general aptitude puzzles (weighing, probability, counting). Most can be solved in five to ten minutes on a whiteboard.
How should I answer a hardware puzzle I have not seen before?
Restate the problem, write down the assumptions, solve a tiny case first (2 bits, 2 cycles), then generalise. Check the answer against one example before you call it done.
Do I need to write Verilog in a puzzle round?
Often yes, for short blocks such as a counter, divider or edge detector. Keep it synthesizable, include reset, and explain the hardware it describes.
Why is a 50% duty cycle divide-by-3 harder than divide-by-2?
An odd divider must hold its output high for a fractional number of input periods (1.5 of 3), which needs both clock edges. Even dividers only need a toggle flop or a counter.
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