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VHDL articles
VHDL
The best free HDL simulators today are Icarus Verilog and Verilator for Verilog and SystemVerilog, and GHDL and NVC for VHDL. All four are open source and actively maintained. If you need a mixed-language or full SystemVerilog simulator at no cost, the free editions that ship with FPGA vendor tools (AMD Vivado's built-in simulator and Questa Altera FPGA Starter Edition) and the browser-based EDA Playground are the practical options. Free H…
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Murugavel Ganesan
March 19, 2023
VHDL
The workplace FSM challenge asks for a three-state machine (S0, S1, S2) that drives y combinationally in S0 and drives z in the cycle after S0, while using as few states, edges, transient states and registers as possible. The minimum answer is three clocked states, four edges, no transient states and two flip-flops: y is a multiplexer of j and k selected by a in S0, and z is simply m in S1 and n in S2, because the state the machine moves to alre…
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Murugavel Ganesan
May 18, 2020
VHDL
The best online VHDL resources today are a handful of long-lived tutorial sites (VHDL-Online, Doulos KnowHow, the UCR "Learn by Example" tutorial), a few classic free texts such as Ashenden's VHDL Cookbook, and free simulators you can run in a browser or on a laptop, such as EDA Playground, GHDL and NVC. Pair one tutorial with one good textbook and a free simulator, and write small designs from the first day. This page keeps the or…
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The Editor's Desk
January 08, 2014
VHDL
Non-synthesizable VHDL is code that simulates correctly but that a synthesis tool cannot turn into gates and flip-flops, or turns into something different from what the simulator showed. The usual culprits are timing delays ( wait for , after ), initial values relied on in ASICs, processes with several different clock conditions, clock edges combined with else or wait , and testbench-only features such as file I/O. The fix is almost always to r…
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Murugavel Ganesan
September 13, 2013
VHDL
1. **For a combinational process in VHDL, the sensitivity list should contain all of the signals that are read in the process. Please give a detailed reason and an exception to this statement.** *Reason:* The sensitivity list in a combinational process specifies the signals that, when changed, should trigger the execution of the process. In VHDL, a combinational process should be sensitive to all the signals that are read within the process t…
VHDL
This article provides a comprehensive methodology that highlights the best practices for mixed-language design integration and automatically comes up with an option for designers to select the optimal method for integration. There are broadly five ways of making mixed-language connections. Pros and cons of each of these approaches and their comparison is described in terms of the usage scenarios, performance implications of using one versus t…
VHDL
ModelSim PE Student Edition was a free, size-limited version of Mentor Graphics' ModelSim HDL simulator for students running VHDL or Verilog coursework on Windows. This post, first published in 2010, records what the Student Edition offered and how it was installed. As of November 2026, Siemens (which now owns the former Mentor Graphics tools) states that the Student Edition is not currently available for download, so the update below lists …
VHDL
Verilog started out as a proprietary simulator in 1984 and enjoyed considerable success due to its C like syntax. In 1990, Cadence Design Systems made the language public. It became an IEEE standard in 1995. VHDL was developed under contract to the U.S. Department of Defense. It became an IEEE standard in 1987. VHDL has its roots in Ada. For many years there was intense competition between Verilog and VHDL for mind share and market share. Both l…
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Aarthi Chinappa
January 17, 2009
VHDL
Transport delay passes every input change to the output after the delay, however short the pulse. Inertial delay also delays the signal, but it filters out pulses shorter than the delay (or a set reject limit), as a real gate does. Delta delay is the zero-time step a VHDL simulator uses to order events that happen at the same simulation time; Verilog orders them through its event scheduling regions instead. Key takeaways Transport delay mode…
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The Editor's Desk
December 21, 2008
VHDL
Hints Avoid more package references than needed Keep all objects and subprograms in the nearest possible scope Keep local objects invisible outside a package Transfer stable component declarations into components packages Re-use functionality of standard packages as much as possible Size of VHDL Units should be reasonable for synthesis A VHDL unit should not exceed 500 lines of code A process or subprogram should not exceed 100 lines of code Com…
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Murugavel Ganesan
January 20, 2008
