U.S. Stimulus Package and the Outsourcing Industry

U.S President Barack Obama signed the $787 billion recovery package into law with a statement that it would "set our economy on a firmer foundation."

Well, all sounds good and cheesy as said! Claims were made that the proposed bailout was the need of the hour and that it was needed very badly and a failure to do so will turn the economic crisis into a catastrophe. But one question everyone had was the moral dilemma that faced the Congress and the White house in the question that if the recipients of the stimulus package should continue to outsource jobs :-). The main objective of the bailout plan was in the creation of jobs for Americans.

Will American citizens only be the sole benefactor of the bailout package? Outsourcing companies outside the U.S. including here in India and the Philippines benefited from the demand of manpower for jobs in consumer services like jobs in research, bill payment and collection, credit analysis and investment banking. The logical conclusion was that companies should be allowed freedom to manage as what they may deem good for their business. Every outsourcing company cannot possibly take all the jobs that a U.S. company requires.

In an era where companies need to stay competitive, not to earn big but just to survive, outsourcing can complement the operations of a company as it is an efficient way to run the company’s operations. The first step a troubled company takes is to save money and instantaneously reduce cost. A company should compare their operations to their competitors to see exactly what is lacking and continuously adapt. There are issues that the stimulus package is not a debate on protectionism and taxpayers are not served well with the continuing export of jobs by the very companies that need the bailout package. The jobs from financial institutions that are in the center of attention are in research, banking and back office.

Meanwhile, President Obama is also aware that revolutions in communication and technology has sent jobs to any place in the world with Internet connection and according to him the fact that the world is more competitive cannot be reversed. Outsourcing of American jobs overseas cannot be reversed and U.S. workers need to compete for jobs with other people on the other side of the globe. This is how globalization is defined. The government must invest in research and innovation to create jobs and industries as the country’s problems on economic front cannot be overcome by building protectionist walls.

In contrast what is speculated to happen in the next couple of months is that, the H1-B's will be laid off in the U.S. This laid off workforce, will be re-hired in India to a great extent in the coming months due to outsourcing by the U.S firms.

Lets wait and see how much the U.S can manage without the H1-B's in general.

Universal phone charger coming

6 ways to help a person who is laid off

In india, being laid off is a taboo. Though most of us have thought through some sort of a plan, it will be foolish to think that gone are the days to pretend this is not happening. I personally having gone through that phase in the US during the last recession, it is somewhat familiar to me in the post-layoff days while saying i am not completely immune.

Today there is a generation of us in the indian workforce, totally unfamiliar with layoffs, and totally unfamiliar with the idea that a job is actually 100% insecure.
The good news about this is that there is not a huge difference between someone laid off and someone not laid off in that all of us feel vulnerable, scared and cheated in some ways.

Which also means that some etiquette has to be followed in that it is different than it used to be for talking to someone who’s been laid off.

1. Never ask "how's the job hunt?" Because the job hunt doesn't change much from day to day, but it's far more demoralizing to report that in someones face.

2. Ask about things like hobbies, kids, and their health – all interesting topics to talk about.

3. Talk about the current affairs & industry news in general - Tell the person what you're working on. Trends you're hearing about. Personnel shifts you've seen. Also, gossip counts as news. Workplace gossip is a positive way to bond. Forget what your mom told you about gossip being bad karma. In this case, gossip equals good karma.

4. Offer atleast one good contact - You need not pretend that connecting in LinkedIn or facebook is going to help his cause, because he should have been building the network long before the layoff loomed. But you could offer up one person you know well who could talk with the person.

5. Acknowledge trouble with the significant other - On this is tricky! More men are getting laid off than women, which puts women in a bad spot because most women choose a husband thinking he'll earn more. Today it's a fair game, and even compassionate to acknowledge.

6. Don't be shy of gratitude - Tell a co-worker who’s been laid off that you miss him or her. And what you miss. It's hard to keep up morale when you're looking for a job. And so often we forget what we are talented at because rejection makes us feel totally un-talented.

SaaS EDA roundtable!

Harry Gries has announced what could be the first SaaS EDA roundtable. He had been discussing this for a while on his blog on how this new trend in IT could be leveraged for the EDA industry and to a sort of feasibilty analysis. This will be held at 2009 DVCon and below are the details.

The SaaS and Cloud Computing Roundtable will be held from 6:30 - 8:00 pm on Wed Feb 25th in the Monterey/Carmel rooms at the San Jose Doubletree Hotel. This is immediately following the DVCon reception down the hall, so grab a drink and a bite and then wander on over.

The format will consist of 5 brief (presentations from people involved in various perspectives in SaaS and cloud computing for EDA:

Free E-Books & Publications

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Standard phone charger?

Why don't our governments force all mobile phone companies to use a single connector on their chargers, in order to eliminate the mountains of e-waste generated by switching chargers every time you switch phones. Transformer bricks with esoteric connectors are the most common form of electronic crap we see on street-vendors' blankets around the world (literally thousands and thousands of them in Mumbai's Chor Bazaar and street and box shops in Bangalore), and given that they all put out nearly the same voltage and amperage, it really does seem like pure waste.

LG first to use Intel's 'Moorestown' chip for smartphone

LG Electronics and Intel have announced a collaboration based on Intel's Moorestown silicon and the Linux Moblin v2.0 software platform at the Mobile World Congress in Barcelona Yesterday. The future LG device, which is being described as a smartphone is expected to be one of the first Moorestown designs to market.

A Brief History of Chip Hype and Flops

[Via Slashdot] On CNet.com, Brooke Crowthers has a review of some flops in the chip-making world — from IBM, Intel, and AMD — and the hype that surrounded them, which is arguably as interesting as the chips' failures.

Why your first design will not work in the field?

“Everyone should get a lecture on why their first design will not work in the field.” Here are some of the very few but primary reasons that getting a single design to work correctly for a few minutes in a lab is much easier than getting thousands of systems to work correctly for months at a time in dozens of countries around the world.

1. Did you forget to force your “unreachable” state to transition to an initial (reset) state? Clock glitches, power surges, radiation, high EM etc will occasionally cause your system to jump to a state that is not defined. When this happens, your design should reset itself, rather than crash or generatel illegal outputs.

2. Do you have internal registers that you cannot access or test? If you can set a register you must have some way of reading the register from outside the chip. In many cases inaccessible or stale registers can cause unexplained system behavior that cannot be debugged. Only full system reset can recover the system to a sane state.

3. Is there any chip in the system that controls your chip? It could be possible that this other chip is buggy. All of your external control lines should be able to be disabled or controlled, so that you can isolate the source of the problem.

4. Not enough decoupling capacitors on your board? The analog world is cruel and very unusual. Voltage spikes, current surges, crosstalk, etc can all corrupt the integrity of digital signals. Trying to save a few cents on decoupling capacitors can cause headaches and significant financial costs in the future.

5. Did you only test your system in the lab, not in the real world? As a product, systems will need to be run for months in the field to encounter all known and unknown issues. Simulation and simple lab testing won’t catch all of the weirdness of the real world. This will be the limit of real world stress test.

6. Did you not adequately test the corner cases and boundary conditions? Every corner case is as important as the main case. Even if some weird event happens only once every six months, if you do not handle it correctly, the bug can still make your system unreliable, unusable and of-course unsellable.

11 arrested, indicted in multi-state visa fraud operation

DES MOINES, Iowa - U.S. Immigration and Customs Enforcement (ICE) agents arrested 11 individuals in seven states Wednesday as part of an investigation into suspected visa and mail fraud. Matthew G. Whitaker, U.S. Attorney for the Southern District of Iowa, announced the operation, which was carried out by federal, state and local law enforcement agencies in Iowa, California, Massachusetts, Texas, Pennsylvania, Kentucky and New Jersey.

Those arrested Wednesday by ICE agents include:
1. Shiva Neeli, arrested in Boston, Mass.; charged with conspiracy and mail fraud.
2. Ramakrishna Maguluri, arrested in Atlanta, Ga.; charged with conspiracy and mail fraud.
3. Villiappan Subbaiah, arrested in Dallas, Texas; charged with conspiracy and mail fraud.
4. Suresh Pola, arrested in Pennsylvania; charged with conspiracy and mail fraud.
5. Vishnu Reddy, arrested in Los Angeles, Calif.; charged with conspiracy, mail fraud and wire fraud.
6. Chockalingam Palaniappan, arrested in San Jose, Calif.; charged with conspiracy, mail fraud and wire fraud.
7. Vijay Myneni, arrested in San Jose, Calif.; charged with conspiracy and mail fraud.
8. Venkata Guduru, arrested in New Jersey; charged with conspiracy and mail fraud.
9. Praveen Andapally, arrested in New Jersey; charged with conspiracy, mail fraud, wire fraud, and making false statements in an immigration matter.
10. Amit Justa, arrested in New Jersey; charged with conspiracy and mail fraud.
11. Karambir Yadav, arrested in Louisville, Ky.; charged with conspiracy and mail fraud.

Ironically all the arrested are Indians, and 7 of the 11 hail from the Indian state of Andhra Pradesh. Follow this link for the official press release from "US Immigration and customs enforcement". Apparently this was waiting to happen given the past history and ease with which these things happen.

Its time for the Indian authorities to take this more seriously.

Why High-k dielectrics in sub 45nm nodes?

To meet the International Technology Roadmap for Semiconductors (ITRS) forecast that device with gate length of sub-10nm will be fabricated by 2016 advanced gate stacks with high-k dielectrics are of intensive research interests. Stringent power requirements in the chips also dictate replacement of silicon dioxide as it has already reached the direct tunneling regime. Currently, many different high-k materials have been explored to replace the silicon dioxide as gate dielectrics. So, what is it that makes High-K dielectrics so attractive in today's technology scaling raodmaps :-)?

In cutting edge silicon nanoelectronics both high-k and low-k dielectrics are needed to implement fully functional and very high-density integrated circuits, although for drastically different reasons. High-k dielectrics are needed in MOS gate stacks to maintain sufficiently high capacitance of the metal (gate)-dielectric-Si structure in MOS/CMOS transistors. Due to the continued scaling of the channel lengths, and hence reduced gate area, the need to maintain sufficient capacitance of the MOS gate stack was met by gradual decrease of the thickness of SiO2 gate oxide Obviously such scaling cannot continue indefinitely as at a certain point gate oxide will become so thin (thinner than about 1 nm) that, due to excessive tunneling current, it would stop playing the role of an insulator. Hence, dielectric featuring k higher than 3.9, i.e. one assuring same capacitive coupling but at the larger physical thickness of the film, must be used instead of SiO2 as a gate dielectric in advanced MOS/CMOS integrated circuits.

On the opposite end of the spectrum finds itself a multi-layer metallization scheme in which inter-layerdielectric (ILD) is used to electrically insulate metal lines. In this case it is of critical importance that the capacitive coupling between adjacent interconnect lines is as limited as possible. Hence, a low-k dielectric must be used to assure as little capacitive coupling (low “cross-talk”) between interconnect lines as possible.

Whether the problem is with high-k dielectrics for MOS gates or low-k dielectrics for ILDs, lack of viable technical solutions in either of these areas will bring any future progress in mainstream silicon technology to a screeching halt. The reliability requirements and challenges of some short-listed high-k dielectrics such as HfO2 and HfSiO2 are widely used by Intel for its 32nm technology nodes for its upcoming processors.

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Every JOB is Temporary - A True Story!

This is a story about Raj, name changed for privacy reasons. When I first met him he was a student and an intern in my team. His personality fit exceptionally well into the culture and he worked very hard while in the company. The job was one that I liken to a grudge job for most of us who had to help fill-in during rush times at our start-up. The task was repeatedly running simulations for many in my team and to collate the results while writing some scripts to ease his job, do an analysis that justifies the purpose of the design and share it with the team. For the most part to start of with, he had no clue what he was doing. The team members were least helpful except for the manager who hired him and who frequently challenged his intellect with logic puzzles that he had no problem with :-)

From an Intern to a full time Design Engineer, the transition was seamless.

Raj stuck with that job through the temporary time which I think was initially 6 months then extended for another 3 months to accommodate for his masters thesis and at the end we offered him a permanent position doing the same tasks! He came on-board and meshed right into the culture. He had built relationships the whole time he was an Intern and the transition to full-time was that much easier since he already had friends at work. His tasks and role remained the same for a while.

At a year of service with the company Raj took on a new role at work. At a start-up there all sorts of opportunities to wear new hats and he transitioned to a bigger role. We were a small group (<10) and didn’t have an official RTL expert in-house. So Raj took on this role while creating new RTL blocks for existing Matlab designs and simultaneously learned Verilog since he came from a VHDL background. As we grew as a company Raj put together FPGA Boards and setup the system setup for system level simulations in a Emulation environment.

But EVERY Job Is Temporary

The hard part of this story is that with the downturn in the economy of 2000-2001 our business had to change to maintain control of our destiny and one of those changes was Raj was laid off along with 50% of our colleagues. The layoffs are fresh in my mind. Good friends, including Raj, who had put in so much sweat equity to stand this company up were suddenly gone. Most of those that were gone pondered daily questioning why and what are they going to do, but Raj’s approach appeared to be the same as when he was an Intern. In his words “I’m looking for the next opportunity”.

In any economy, but especially one like our current situation take any position you can get and once you get in look for those opportunities that allow you to shine. All jobs/positions are created because there is a need within the company. So if it’s running simulations blindly or writing trivial scripts that challenge the intellect of you superiors, give it your best and create a place for yourself within the organization.

Job Posting: Firmware Development - ADSL CPE

Location: Bangalore, India
Experience: 3+ Years
Education: Bachelors degree in ECE or EEE
Skill Set:
  1. Proficiency in C.
  2. Experience in DSP with OFDM, physical layer communications, wireless communication.
  3. Experience in xDSL technology and firmware greatly desired.
  4. Experience in xDSL testing, WT100, TR-67, use of Spirent equipment, familiarity with TCL scripts, ATE would be a plus!
  5. Exposure to G.992.3 (ADSL2) & G.992.5 (ADSL2+) standards preferred!
Send in your resumes to:
onenanometer+jobs [at] gmail [dot] com

Chip Art - Through History

These chip art images were either extracted through lapping techniques, magnification and/or Polaroid capturing. Typically chips have a unique "signature" or a identification number to recognize and expect to be logic, memory, gates, or a product of some kind. However, these signatures are the designer's, the engineer's and in some cases a company logo. They have left their mark in and for history. The chip collection is complemented with imagination which takes no space on a shelf, requires no conservation and cannot typically be exhibited.

... a historical and operational perspective on how these photographs are captured: laboratory engineers and technicians capture these images on a catch-as-catch-can basis... many of these photographs are years old and cannot be [easily] identified... the images were simply posted on a board and then [staff] went about the business at hand ... - Integrated Circuit Engineering Corporation

Check out this link for more pictures :-)

Digital Electronics: On Wikipedia

Please help improve the "Digital Electronics" Article on Wikipedia by contributing. Please don't simply delete the existing section or update the information without prior discussing on the talk page! We have observed that lots of unnecessary changes have happened in the last 1 yr or so. Though by definition it is "anyone can update", please don't link to your personal pages or blogs!!!!!

As per wikipedia...
This article includes a list of references or external links, but its sources remain unclear because it lacks inline citations. Please improve this article by introducing more precise citations where appropriate.
This article or section has multiple issues. Please help improve the article or discuss these issues on the talk page.It needs additional references or sources for verification.

Semiconductor Hall Of Fame - Zhores I. Alferov

Development of semiconductor heterostructures used in high-speed and opto-electronic systems; The Nobel Prize in Physics 2000.

Zhores I. Alferov was born in Vitebsk, Belorussia, USSR, on March 15, 1930. In 1952, he graduated from the Department of Electronics of V. I. Ulyanov (Lenin) Electrotechnical Institute in Leningrad. Since 1953 he has been a staff member of the Physico-Technical Institute where he held consecutively the following positions: junior researcher (1953–1964), senior researcher (1964–1967), head of the laboratory (1967–1987), director (1987–present). He earned scientific degrees: a candidate of sciences in technology in 1961 and a doctor of sciences in physics and mathematics in 1970, both from the Ioffe Institute.

Since 1962 he has been working in the area of III–V semiconductor heterostructures. His outstanding contributions to physics and technology of III–V semiconductor heterostructures, especially investigations of injection properties, development of lasers, solar cells, LED's, and epitaxy processes have led to the creation of modern heterostructure physics and electronics.

In 1973 Zh. I. Alferov took over the chair of optoelectronics at the St Petersburg State Electrotechnical University (former V. I. Ulyanov (Lenin) Electrotechnical Institute) and in 1988 he was appointed to Dean of the Faculty of Physics and Technology at the St Petersburg Technical University.

He was elected a corresponding member of the USSR Academy of Sciences in 1972 and Academy's full member in 1979. From 1989 onward, he has been Vice-President of the USSR (Russian) Academy of Sciences and President of its St Petersburg Scientific Center.

He is Editor-in-Chief of a Russian journal, Pis'ma v Zhurnal Tekhnicheskoi Fiziki (English-language version—Technical Physics Letters) and a member of the Editorial Board of a Russian journal Nauka i Zhizn' (Science and Life).

Zh. I. Alferov is author of 4 books, 400 articles, and 50 inventions on semiconductor technology.

Read his Full Bio @ Nobelprize.org

Semiconductor Education in High School

Any ideas or opinions or even suggestions to teach and promote semiconductors at the high school level will be greatly appreciated in today's world? It is in this spirit that i am directing your attention to a site that is teaching 16+ years olds what semiconductors are all about.

Semiconductors - A piece of history

From Bell labs to silicon Valley: A saga of semiconductor technology transfer, 1955-61*
See how it all happened! Link Here (PDF, 675K)

Why the layoffs if we're still profitable?

This is the most common question being asked among engineers and rather should be asking if you are not. EDN Executive Editor Ron Wilson Explores "We see giant companies like IBM and Microsoft announce great fourth-quarter and annual results, and then follow up with a layoff announcement." We see smaller companies in the fabless world staying on track on product development, successfully sampling to key customers, and ramping revenue products—doing everything right—suddenly making significant cutbacks, either laying off people or cutting back on projects that lead to layoffs elsewhere. And we see, if we look carefully, start-ups who are on track and meeting milestones just shutting their doors. What gives?" Read Ron's complete post on EDN to understand behind the scenes financial opera of a typical Industry Giant!

Semiconductor Job Outlook

With big players joining the fray in job cuts, the semiconductor job outlook looks atrociously grim. The recent figures and estimates suggest that this recession is one that was not witnessed before and here to stay. The list below gives the more recent jobcuts and updates.
If you are someone who is affected by this crazy economy, you are not alone. Everyday millions of people, not just in the semiconductor business but in all industries go to work without knowing if their job is safe.

Is there a practical solution to end this carnage quickly? I don't think so! We just have to ride it out.

Wikipedia: The Missing Manual

Wikipedia: The Missing Manual is a popular how-to book on Wikipedia that has all the information you need to get started with editing pages on Wikipedia. Wikipedia may be the biggest group writing project ever, but the one thing you won't find in the comprehensive online encyclopedia is easy-to-follow guidance on how to contribute. Wikipedia: The Missing Manual helps you avoid beginners' blunders and gets you sounding like a pro from your first edit. It also gives you advise on creating articles, and working with the Wikipedia community to review new articles, mediate disputes, and maintain the site.
The book sells for $29.99 on Amazon but the publishers have uploaded the entire book to Wikipedia website under the GNU license. You can read the book for free, even lets you copy, translate and distribute the book in any format provided the derivative work is also free.

And like all the other pages on Wikipedia, this new "Wikipedia: The Missing Manual" Wikipedia section is open for public editing.

The Seven Habits of Highly Effective People

You can Download a free copy of "The Seven Habits of Highly Effective People" audio book by going to audible.com. To avail this offer, make sure that you select "USA" as the country when creating a free audible account on the next page.

The Seven Habits of Highly Effective People has sold more than 15 million copies worldwide while the audio version was the first non-fiction audio book in U.S. publishing history to sell more than one million copies according to Wikipedia.

Upcoming Events: Automated Design of Digital Microfluidic Lab-on-Chip

An event of VLSI Society of India!
Seminar on: Automated Design of Digital Microfluidic Lab-on-Chip (Connecting Biochemistry to Information Technology and Electronic Design Automation)
Speaker: Prof. Krishnendu Chakrabarty, Dept of ECE, Duke University
Date and Venue: 11 February, 2009, 11:00AM-12:00PM, G1, TI India Campus, Bangalore
For Details click here!

Free E-Book Download - Only RSS Subscribers!

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E-Book: The Digital Signal Processing Handbook. Read further to find out how!

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What will be your engineering legacy?

It is no easy task to record the achievements of individual engineers nowadays. But looking at the past achievements and trends, most of them have had graduated from schools like MIT, Stanford, IITs etc. and joined a handful of companies that offered superb training grounds and career opportunities.

Checkout this article on EETimes

The Top 10 power management 'How To' design articles of 2008

EETimes has published an article on the Top 10 Power Management articles of 2008. {Follow Here}

Salary and Job Satisfaction

I picked up this survey from the web and thought should share. What do you think?[Article Here]

Advertise with us!

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Top Ten Chip Companies 2008

Based on Revenue numbers from iSuppli in $Bn.

1. Intel - 34
2. Samsung - 18
3. TI - 12
4. Toshiba - 11
5. ST - 10.7
6. Renesas - 8
7. Sony - 7
8. Qualcomm - 6.7
9. Hynix - 6.4
10. Infineon - 6.3

How to run a semiconductor company?

Anybody in this industry would agree that there are 3 things that are critical for its success.
1. Quick adaptation of Technology - Can impact chip cost, time to market and customer/market reputation! Even transfer of new technology from Engineering to production.
2. Being ahead of the competition - Bad marketing decisions and late changes in the design can adversely affect this motive. Smart decisions can avoid a critical delay. Definition of responsibilities upfront can save the project and money.
3. Making Engineers work with pride - Not just defining statement of work and schedules.Give them opportunities to interact with with other levels of management and production. Make them confident.

How many companies follow these three tenets? How many have ignored? How many have been successful? How many have failed?

Please comment with your views and experiences and lets figure of out the root cause of failure and success togather.

"Semiconductors are like a new hit song, composed on an old classical theme", writes the legendary former CEO of Toshiba Semiconductors Tsuyoshi Kawanishi in his book 'Chip Management, "What I mean by this is that the applications for semiconductors are nearly infinite, but the basic technology itself is classic".

Top 10 Ways to Save Money in a Recession

Times are tough, money's tight, and nobody should be spending more than they need. If you think you've exhausted all avenues for saving a buck, check out lifehacker's ten suggestions for saving money in a recession.

VITAL and its Origins!

Verilog started out as a proprietary simulator in 1984 and enjoyed considerable success due to its C like syntax. In 1990, Cadence Design Systems made the language public. It became an IEEE standard in 1995. VHDL was developed under contract to the U.S. Department of Defense. It became an IEEE standard in 1987. VHDL has its roots in Ada.

For many years there was intense competition between Verilog and VHDL for mind share and market share. Both languages have their strong points. In the end, most EDA companies came out with simulators that work with both. Early in the language wars it was noted that Verilog had a number of built-in, gate-level primitives. Over the years these had been optimized for performance by Cadence and later by other Verilog vendors. Verilog also had a single defined method of reading timing into a simulation from an external file. VHDL, on the other hand, was designed for a higher level of abstraction. Although it could model almost anything Verilog could, and without primitives, it allowed things to be modeled in a multitude of ways. This made performance optimization or acceleration impractical. VHDL was not successfully competing with Verilog as a sign-off ASIC language. The EDA companies backing VHDL saw they had to do something. The something was named VITAL, the VHDL Initiative toward ASIC Libraries.

The intent of VITAL was to provide a set of standard practices for modeling ASIC primitives, or macrocells, in VHDL and in the process make acceleration possible. Two VHDL packages were written: a primitives package and a timing package. The primitives package modeled all the gate-level primitives found in Verilog.

Because these primitives were now in a standard package known to the simulator writers, they could be optimized by the VHDL compilers for faster simulation. The timing package provided a standard, acceleratable set of procedures for checking timing constraints, such as setup and hold, as well as pin-to-pin propagation delays. The committee writing the VITAL packages had the wisdom to avoid reinventing the wheel. They chose the same SDF file format as Verilog for storing and annotating timing values.

SDF is the Standard Delay Format, IEEE Standard 1497. It is a textual file format for timing and delay information for digital electronic designs. It is used to convey timing and delay values into both VHDL and Verilog simulations. Another stated goal of VITAL is model maintainability. It restricts the writer to a subset of the VHDL language and demands consistent use of provided libraries. This encourages uniformity among models, making them easily readable by anyone familiar with VITAL. Readability and having the difficult code placed in a provided library greatly facilitate the maintenance of models by engineers who are not the original authors.

VITAL became IEEE Standard 1076.4 in 1995. It was reballoted in 2000. The 2000 revision offers several enhancements. These include support for multisource interconnect timing, fast path delay disable, and skew constraint timing checks. However, the most important new feature is the addition of a new package to support the modeling of static RAMs and ROMs.

Author: Keshav K, MindTree, Bangalore, India

Post a link in your comments!

I am sure you have been reading this blog and did you decide to comment? In writing your comment, you may find a need to post a reference link which may be a website or an article on the internet or just a link to your blog or website or article.

Just how easy is to do that? Well, it is simple. This is the code that you need to drop into the comment box:

Replace the URL with the URL of the site or article you are linking to and replace the Title with the title of the site or artcle.

Ps: When you place a link in the comments, it is as good as we linking to you. Now get out there and comment!!! Thats our motivation.

Thai Pongal, Makara Sankranti & Tamil New Year Greetings!

We wish all our reader a very happy Thai Pongal, Makara Sankaranti and Tamil New Tear(இனிய தமிழ் புத்தாண்டு நல்- வாழ்த்துக்கள்) 2009!

Memories - Memory Faults - Part 4

As memories grow larger, with more memory cells packed into an ever-shrinking die area, the cost to manufacture a die remains fairly constant, while the time it takes to apply test programs increases exponentially. It is estimated that the cost to test a memory chip runs from 50% to 70% of the total cost of the finished product. The first steps in reducing the cost of memory test is to understand what fault mechanisms are most likely to occur and then develop test programs that target those faults. With this approach, the manufacturer and the end-user can determine their priorities, balancing cost versus DPM (defects per million) that they can tolerate in their applications.

A number of different failure types can occur in semiconductor memories, affecting memory cell contents, cell addressing, and the time required to read out data. Some of the more common failures include the following:

Cell opens or shorts
Address non uniqueness
Cell/column/row disturb sensitivity
Sense amplifier interaction
Slow access time
Slow write recovery
Data sensitivity
Refresh sensitivity
Static data losses

Opens and shorts within semiconductor memory cells may occur because of faulty processing, including misaligned masks or imperfect metallization. These failures are characterized by a general randomness in their nature. Opens and shorts may occur at the chip connections to a printed circuit board. In a km × n memory system containing km words of n bits each, and made up of memory chips of size m × 1, a fault that occurs in bit position i of m consecutive bits is indicative of either a totally failed chip or one in which an open or short exists between the chip and the PCB on which it is mounted.

Address non-uniqueness results from address decoder failures that may either cause the same memory cell to be accessed by several different addresses or several cells may be addressed during a single access. These failures often cause some cells to be physically inaccessible. An effective test must insure that each read or write operation accesses one, and only one, memory cell.

Disturb sensitivity between adjacent cells or between cells in the same row or column can result from capacitive coupling. Slow access time can be caused by slow decoders, overloaded sense amplifiers, or an excessive capacitive charge on output circuits. Slow write recovery may indicate a saturated sense amplifier that cannot recover from a write operation in time to perform a subsequent read operation.

A memory cell can be affected by the contents of neighboring cells. Worse still, the cell may be affected only by particular combination's on neighboring cells. This problem grows more serious as the distance between neighboring cells shrinks. Refresh sensitivity in dynamic RAMs may be induced by a combination of data sensitivity and temperature or voltage fluctuations. Static RAM cells are normally able to retain their state indefinitely. However, data may become lost due to leakage current or opens in resistors or feedback paths.

By contrast, when we look at faults in random logic, that fault models other than the stuck-at model were examined. The one trait these models had in common was a susceptibility to combinatorial explosion. For very small circuits, the number of faults grew so quickly that it was simply not feasible to consider them. Memory circuits, because of their density and the close proximity of cells to one another, exhibit this problem of combinatorial explosion to a far greater degree. Hence, it becomes necessary to restrict consideration to faults that are most likely to occur.

The first step is to group the faults into three broad categories: address decoder faults, memory array faults, and read/write logic faults. From there we use the fact, that faults in memory addressing and read/write logic, which includes sense amplifiers, write drivers, and other supporting logic, can be mapped onto functionally equivalent faults in the memory array. This makes it possible to concentrate on faults in the memory array and to develop tests addressed at the functionality of the memory array.

First consider faults in the address decode logic. A fault may cause multiple cells to be accessed, or no cell may be accessed, or the wrong cell may be addressed. In the case of multiple cells being addressed, the fault may be viewed as a coupling fault between cells. If no cell is addressed, then, depending on the logic, the response from the read logic may appear as a stuck-at-1 or a stuck-at-0. If the wrong cell is addressed, then, given the presence of the opposite value in that cell, it appears as a stuck-at fault.

A fault in the read/write logic may cause an output line to be stuck-at-0 or stuckat-1. In either case, the corresponding cell may be considered to be stuck-at-0 or stuck-at-1. If there are shorts or capacitive coupling between data input or data output lines, these faults can be regarded as coupling between memory cells.

Author Disclaimer:
All the information depicted in these articles have been collated from different sources using google search and for non commercial, educational purposes only. If you think we have violated any copyright please inform us and we will correct them in our capacity, as soon as possible.

Article submitted by:
Murali of IBM

Memories - Test Patterns & Algorithms - Part 3

In this section some classical, or legacy, memory test algorithms will be examined. Memory test algorithms fall into two categories: functional and dynamic. A functional test targets defects within a memory cell, as well as failures that occur when cell contents are altered by a read or write to another cell. A dynamic test attempts to find access time failures. The All 1s or All 0s tests are examples of functional tests. These tests write 1s or 0s into all memory cells in order to detect individual cell defects including shorts and opens. However, these tests are not effective at finding other failure types.

A memory test pattern that tests for address nonuniqueness and other functional faults in memories, as well as some dynamic faults, is the GALPAT (GALloping PATtern), sometimes referred to as a ping-pong pattern. This pattern accesses each address repeatedly using, at some point, every other cell as a previous address. It starts by writing a background of zeroes into all memory cells. Then the first cell becomes the test cell. It is complemented and read alternately with every other cell in memory. Each succeeding cell then becomes the test cell in turn and the entire read process is repeated. All data are complemented and the entire test is repeated. If each read and compare is counted as one operation, then GALPAT has an execution time proportional to 4N^2, where N is the number of cells. It is effective for finding cell opens, shorts, address uniqueness faults, sense amplifier interaction, and access time problems.

Walking Pattern is similar to the GALPAT except that the test cell is read once and then all other cells are read. To create a Walking Pattern from the GALPAT program, omit the second read operation in the testbench. The Walking Pattern has an execution time proportional to 2N^2 . It checks memory for cell opens and shorts and address uniqueness.

March, like most of the algorithms, begins by writing a background of zeroes. Then it reads the data at the first location and writes a 1 to that address. It continues this read/write procedure sequentially with each address in memory. When the end of memory is reached, each cell is read and changed back to zero in reverse order. The test is then repeated using complemented data. Execution time is of order N. It can find cell opens, shorts, address uniqueness, and some cell interactions.

Galloping Diagonal is similar to GALPAT in that a 1 is moved through memory. However, it is moved diagonally, checking both row and column decoders simultaneously. It is of order 4N3 /2. Row and column GALPATs of order 4N^(3/2) also exist. Sliding Diagonal (see Figure) writes a complete diagonal of 1s against a background of 0s and then, after reading all memory cells, it shifts the diagonal horizontally. This continues until the diagonal of 1s has passed through all memory locations. The Diagonal test, of order N, will verify address uniqueness at a signifi-cant speed enhancement over the Walk or GALPAT.

Surround Read Disturb starts by creating a background of all 0s. Then, each cell in turn becomes the test cell. The test cell is complemented and the eight physically adjacent cells are repeatedly read. After a number of iterations the test cell is read to determine if it has been affected by the read of its neighbors. The operation is then repeated for a background of 1s. The intent is to find disturbances caused by adjacent cell operations. Execution time depends on the number of read cycles but is of the order N. Surround Write Disturb is identical to the Surround Read Disturb except that a write rather than a read is performed.

Write Recovery writes a background of 0s. Then the first cell is established as the test cell. A 1 is written into the second cell and the first (test) cell is read. The second cell is restored to 0 and the test cell is read again. This is repeated for the test cell and every other cell. Every cell then becomes the test cell in turn. The entire process is repeated using complemented data. This is an N^2 test that is directed at write recovery type faults. It also detects faults that are detected by GALPAT.

Address Test writes a unique value into each memory location. Typically, this could be the address of that memory cell; that is, the value n is written into memory location n. After writing all memory locations, the data are read back. The purpose of this test is to check for address uniqueness. This algorithm requires that the number of bits in each memory word equal or exceed the number of address bits.

Moving Inversions test inverts a memory filled with 0s to 1s and conversely. After initially filling the memory with 0s, a word is read. Then a single bit is changed to a 1, and the word is read again. This is repeated until all bits in the word are set to 1 and then repeated for every word in memory. The operation is then reversed, setting bits to 0 and working from high memory to low memory. For a memory with n address bits the process is repeated n times. However, on each repetition, a different bit of the address is taken as the least significant bit for incrementing through all possible addresses. An overflow generates an end around carry so all addresses are generated but the method increments through addresses by 1s, 2s, 4s, and so on. For example, on the second time through, bit 1 (when regarding bit 0 as least significant bit, LSB) is treated as the LSB so all even addresses are generated out to the end of memory. After incrementing to address 111...110, the next address generated is address 000...001, and then all consecutive odd addresses are generated out to the end of memory. The pattern of memory address generation (read the addresses vertically) for the second iteration is as follows:

0000 . . . 1111
. . .
. . .
. . .
0000 . . . 1111
0011 . . . 0011
0101 . . . 0101
0000 . . . 1111

The Moving Inversions test pattern has 12BNlog2^N patterns, where B is the number
of bits in a memory word. It detects addressing failures and cell opens and shorts. It is also effective for checking access times.

To be continued...
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Launch - I have something to explain (updated)

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Memories - Memory Types - Part 2

Semiconductor memories are characterized according to the following properties:
Serial or random access, Volatile or nonvolatile, Static or dynamic, Destructive or nondestructive readout.

Serial access memories are those in which data are accessed in a fixed, predetermined sequence. Magnetic tape units are an example of serial access. To read a record it is necessary to read the entire tape up to the point where the desired data exists.

By way of contrast, a random access memory (RAM) permits reading of data at any specific location without first reading other data. When performing a read of a FIFO (first-in, first-out) memory, the first location stored is the first to be read out.

These memories act as buffers when transferring data between functional units with different data rates. A stack in a computer, often used to save data and return addresses, is an example of a LIFO (last-in, first-out) memory. The last data pushed onto the stack is the first data to become available when the stack contents are popped from the stack.

Memories are categorized according to whether or not they can retain information when power is removed.

A nonvolatile memory can retain information when power is removed. Examples of nonvolatile memories include magnetic cores, magnetic tapes, disks, MROMs, EPROMS, EEPROMS, and flash memories.

Volatile memory devices lose information when power is removed. Volatile memories can be further broken down into static and dynamic memories.

A static memory retains information as long as power is applied, while a dynamic memory can lose information even when power is continuously applied. Static RAMs (SRAMs) are flip-flops that, with their two stable states, can remain in a given state indefinitely, without need for refresh, as long as power is applied; that is, they are static but volatile.

The dynamic RAM (DRAM), illustrated in Figure, is an example of a dynamic memory. The cell is chosen if decoding the memory address causes its wordline to be selected. It is basically a capacitor that can either be discharged onto the bitline or that can be recharged from the bit-line. Since it is a capacitor, the charge can leak away over time. The memory system must employ refresh circuitry that periodically reads the cells and writes back a suitably amplified version of the signal. If the contents of a memory device are destroyed by a read operation, it is classified as a destructive readout (DRO); otherwise it is a nondestructive readout (NDRO) device.

DRAMs must be refreshed when their contents are read out, since a read causes the capacitor to discharge. Programmable read-only memories (PROMs) are slightly more complicated to characterize. They are static and nonvolatile. Mask programmable ROMs and fuse programmable ROMs are programmed once and thereafter can only be read.

EPROMs (erasable PROMs) can be erased by means of ultraviolet light, which involves physically removing them from the system in which they are installed. For all practical purposes, they are programmed only once because it is quite inconvenient to erase and reprogram them, unless they are being used to emulate a new design for the purposes of debugging that design.

EEPROMs (electrically erasable PROMs) can be reprogrammed after being installed in a system, but their response time is slower than DRAMs or SRAMs; hence they are confined to applications where nonvolatility is required.

Flash memories are structurally almost identical to EPROMs, but they can be reprogrammed in a system and are more dense than EEPROMs. However, EEPROMs can be programmed a bit at a time, whereas flash memories are erased a block at a time before being reprogrammed. The Venn diagram in Figure illustrates this distribution of properties among the various kinds of semiconductor memories.

To be continued...

Memories - Introduction - Part 1

Memories are pervasive in digital computing. Consider, the personal computer which has a main memory, video memory, translation ROMs, shadow ROMs, scratchpad memory, hard disk, floppy disk, CDROM, and various other kinds of storage distributed throughout. In addition, the die that contains the microprocessor also contains one or more levels of cache.

A typical PC is depicted in the block diagram below. It is basically a memory hierarchy connected by several buses and adapters and controlled by a CPU. The purpose for much of the hierarchy is to combine two or more storage systems with divergent capacities, speeds, and costs such that the combined system has almost the speed of the smaller, faster, more expensive memory at almost the cost, speed, and storage capacity of the larger, slower, less expensive memory. Clearly, not all storage devices are part of this hierarchy.

The CDROM may be used to deliver programs and/or data to an end user, and video memory is dedicated to the display console. The central processing unit (CPU) accesses many of these auxiliary memory devices through a peripheral component interconnect (PCI) bus, which regulates the flow of data through the system. Unlike the random logic that has been considered up to this point, memory storage devices are characterized by a high degree of regularity. For example, a semiconductor memory is organized as an array of cells, while storage on a hard drive is organized into cylinders. This regularity of semiconductor memories permits much greater packing of transistors on die. For example, in the PowerPC MPC750, memory accounts for 85% of the transistors but only 44% of the die area. In the Alpha 21164, 80% of the 9.6 million transistors are used for three on-chip caches, but the remaining 20% of the transistors occupy a majority of the physical die area. The various storage devices in the Figure above employ different kinds of circuits for storing and retrieving data, and different kinds of media for retaining data, hence they have unique failure mechanisms, that require different test strategies. These memories may also employ varying levels of redundancy to detect and/or correct errors during operation.

To be continued...


Got a question? Ask in the Forums

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Featured on DFT Digest!

Though this post is late by almost 15 days i feel obligated to acknowledge the reference to a great series on "the economics of test" on this Blog.

John Ford of DFT digest has indeed appreciated much of the information shared on this series of posts while humorously pointing out the mistake in the name of the city of Nice, France :-). It was indeed a mistaken repetitive occurrence during copy paste! Thanks Bauer and John for pointing this out.

Blog Updates, Top 10 Features additions!

Hello Reader,
In this New year we are happy to announce a significantly redesigned blog which gives more flexibility and control to all. Fortunately most of the features are available only when subscribed, either by RSS or by E-MAIL.

Top 10 features:
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Happy New Year 2009!

We wish all our readers a very Happy New Year 2009!

9 yr old Indian girl is the youngest Microsoft Certified Professional

A nine year-old Indian girl named M. Lavinashree has passed the Microsoft Certified Professional Exam, becoming the youngest person to ever pull it off (smashing the record previously held by a 10 year-old Pakistani girl). The youngster has a long history of making records in her short life -- including reciting all 1,300 couplets of a 2,000 year-old Tamil epic at the age of three -- and now she's now cramming for the Microsoft Certified Systems Engineer Exam.

The person with the certificate in hand is none other than the former Indian President Dr. APJ Abdul Kalam (Missile Scientist and Former DRDO - Defense Research and Development Organization, India, Director)

[Via: TechNews]

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The Economics of Test, Part - IV

Detecting a defective unit is often only part of the job. Another important aspect of test economics that must be considered is the cost of locating and replacing defective parts. Consider again the board with 10 integrated circuits. If it is found to be defective, then it is necessary to locate the part that has failed, a time-consuming and error-prone operation. Replacing suspect components that have been soldered onto a PCB can introduce new defects. Each replaced component must be followed by retest to ensure that the component replaced was the actual failing component and that no new defects were introduced during this phase of the operation. This ties up both technician and expensive test equipment. Consequently, a goal of test development must be to create tests capable of not only detecting a faulty operation but to pinpoint, whenever possible, the faulty component. In actual practice, there is often a list of suspected components and the objective must be to shorten, as much as possible, that list.

One solution to the problem of locating faults during the manufacturing process is to detect faulty devices as early as possible. This strategy is an acknowledgment of the so-called rule-of-ten. This rule, or guideline, asserts that the cost of locating a defect increases by an order of magnitude at every level of integration. For example, if it cost N dollars to detect a faulty chip at incoming inspection, it may cost 10N dollars to detect a defective component after it has been soldered onto a PCB. If the component is not detected at board test, it may cost 100 times as much if the board with the faulty component is placed into a complete system. If the defective system is shipped to a customer and requires that a field engineer make a trip to a customer site, the cost increases by another power of 10. The obvious implication is that there is tremendous economic incentive to find defects as early as possible. This preoccupation with finding defects early in the manufacturing process also holds for ICs.27 A wafer will normally contain test circuits in the scribe lanes between adjacent die. Parametric tests are performed on these test circuits. If these tests fail, the wafer is discarded, since these circuits are far less dense than the circuits on the die themselves. The next step is to perform a probe test on individual die before they are cut from the wafer. This is a gross test, but it detects many of the defective die. Those that fail are discarded. After the die are cut from the wafer and packaged, they are tested again with a more thorough functional test. The objective? Avoid further processing, and subsequent packaging, of die that are clearly defective.

About the Author:
Name: Joachim Bauer, Test Engineer
Experience: 13+ Yrs
Location: Nice, France

The Economics of Test, Part - III

However, if devices are tested, feature sizes can be reduced and more die will fit on each wafer. Even after the die are tested and defective die are discarded, the number of good die per wafer exceeds the number available at the larger feature sizes. The benefit in terms of increasing numbers of good die obtainable from each wafer far outweighs the cost of testing the die in order to identify those that are defective. Point B on the graph corresponds to a point where process yield is lower than the required quality level. However, testing will identify enough defective units to bring quality back to the required quality level. The horizontal distance from point A to point B on the graph is an indication of the extent to which the process capability can be made more aggressive, while meeting quality goals. The object is to move as far to the right as possible, while remaining competitive. At some point the cost of test will be so great, and the yield of good die so low, that it is not economically feasible to operate to the right of that point on the solid line.

We see therefore that we are caught in a dilemma: Testing adds cost to a product, but failure to test also adds cost. Trade-offs must be carefully examined in order to determine the right amount of testing. The right amount is that amount which minimizes total cost of testing plus cost of servicing or replacing defective components. In other words, we want to reach the point where the cost of additional testing exceeds the benefits derived. Exceptions exist, of course, where public safety or national security interests are involved.

Another useful side effect of testing that should be kept in mind is the information derived from the testing process. This information, if diligently recorded and analyzed, can be used to learn more about failure mechanisms. The kinds of defects and the frequency of occurrence of various defects can be recorded and this information can be used to improve the manufacturing process, focusing attention on those areas where frequency of occurrence of defects is greatest.

This test versus cost dilemma is further complicated by “time to market.” Quality is sometimes seen as one leg of a triangle, of which the other two are “time to market” and “product cost.” These are sometimes posited as competing goals, with the suggestion that any two of them are attainable.25 The implication is that quality, while highly desirable, must be kept in perspective. Business Week magazine, in a feature article that examined the issue of quality at length, expressed the concern that quality could become an end in itself. The importance of achieving a low defect level in digital components can be appreciated from just a cursory look at a typical PCB. Suppose, for example, that a PCB is populated with 10 components, and each component has a defect level DL = 0.999. The likelihood of getting a defect free board is (0.999)10 = 0.99004; that is, one of every 100 PCBs will be defective—and that assumes no defects were introduced during the manufacturing process. If several PCBs of comparable quality go into a more complex system, the probability that the system will function correctly goes down even further.

About the Author:
Name: Joachim Bauer, Test Engineer
Experience: 13+ Yrs
Location: Nice, France

The Economics of Test, Part - II

The table depicted shows test cost broken down into four categories some of which are one-time, non recurring costs whereas others are recurring costs. Test preparation includes costs related to development of the test programs as well as some potential costs incurred during design of the DFT features.

DFT-related costs are directed toward improving access to the basic functionality of the design in order to simplify the creation of test programs. Many of the factors depicted in the Figure imply both recurring and nonrecurring costs. Test execution requires personnel and equipment. The tester is amortized over individual units, representing a recurring cost for each unit tested, while costs such as probe cards may represent a one-time, nonrecurring cost. The testrelated silicon is a recurring cost, while the design effort required to incorporate testability enhancements, listed under test preparation as DFT design, is a nonrecurring cost.

The category listed as imperfect test quality includes a subcategory labeled as tester escapes, which are bad chips that tested good. It would be desirable for tester escapes to fall in the category of nonrecurring costs but, regrettably, tester escapes are a fact of life and occur with unwelcome regularity.

Lost performance refers to losses caused by increases in die size necessary to accommodate DFT features. The increase in die size may result in fewer die on a wafer; hence a greater number of wafers must be processed to achieve a given throughput. Lost yield is the cost of discarding good die that were judged to be bad by the tester.

The column in Figure labeled “Volume” is a critical factor. For a consumer product with large production volumes, more time can be justified in developing a comprehensive test plan because development costs will be amortized over many units. Not only can a more thorough test be justified, but also a more efficient test—that is, one that reduces the amount of time spent in testing each individual unit. In low-volume products, testing becomes a disproportionately large part of total product cost and it may be impossible to justify the cost of refining a test to make it more efficient. However, in critical applications it will still be necessary to prepare test programs that are thorough in their ability to detect defects.

A question frequently raised is, “How much testing is enough?” That may seem to be a rather frivolous question since we would like to test our product so thoroughly that a customer never receives a defective product. When a product is under warranty or is covered by a service contract, it represents an expense to the manufacturer when it fails because it must be repaired or replaced. In addition, there is an immeasurable cost in the loss of customer goodwill, an intangible but very real cost, not reflected in the Figure, that results from shipping defective products. Unfortunately we are faced with the inescapable fact that testing adds cost to a product. What is sometimes overlooked, however, is the fact that test cost is recovered by virtue of enhanced throughput. Consider the graph in the Figure. The solid line reflects quality level, in terms of defects per million (DPM) for a given process, assuming no test is performed. It is an inverse relationship; the higher the required quality, the fewer the number of die obtainable from the process. This follows from the simple fact that, for a given process, if higher quality (fewer DPM) is required, then feature sizes must be increased. The problem with this manufacturing model is that, if required quality level is too high, feature sizes may be so large that it is impossible to produce die competitively. If the process is made more aggressive, an increasing number of die will be defective, and quality levels will fall. Point A on the graph corresponds to the point where no testing is performed. Any attempt to shrink the process to get more units per wafer will cause quality to fall below the required quality level.

About the Author:
Name: Joachim Bauer, Test Engineer
Experience: 13+ Yrs
Location: Nice, France