Interview Questions
Fifo depth calculation
A First-In-First-Out (FIFO) depth calculation is a crucial aspect of designing and implementing FIFO buffers or queuing…
AMBA
Advanced Microcontroller Bus Architecture (AMBA)
Advanced Microcontroller Bus Architecture (AMBA): Description: The AMBA™ on-chip interconnect system is an established …
SOC
SOC interconnect Bus
SOC interconnect bus: These buses are used within a chip to interconnect an different IP cores to the surrounding inter…
I2C
I2C bus
The Inter-IC bus, commonly known as the I²C ("eye-squared-see") bus, is a control bus that provides the commu…
HDLC
HDLC (High-level Data Link Control)
HDLC is a bit-oriented, link layer protocol for the transmission of data over synchronous networks. It is an ISO standa…
Verification
Types of Timing Verification
Dynamic timing: The design is simulated in full timing mode. Not all possibilities tested as it is dependent on the inp…
Delays
Types of Delays
Intrinsic device delay: Time taken for the cell to change state due to a change on the input pins. Interconnect delay: …
skew
All about Clock skew & Short path
Clock Skew: Differences in clock signal arrival times across the chip are called clock skew. It is a fundamental design…
Interview Questions
Interview Questions (Intel)
# Have you studied buses? What types? Ans: 1. Processor-Memory Bus, I/O Bus, System Bus, Backplane Bus. # Have you s…
What are Embedded Systems?
Any electronic system that uses a CPU chip, but that is not a general-purpose workstation, desktop or laptop computer. …
Tristate
Tristate Buffers
You can think of tristate buffers as a way of turning a signal on and off. When the enable input at the top of the buff…
RTL
behavioral & RTL
Multi-cycle functionality: It is a fundamental characteristic of synthesizable RTL code that the complete functionality…
Timing
Clock Latency & clock skew
Clock latency means, the number of clock pulses required by the ckt to give out the first output. Generally we will obs…
mux
gates from mux's
OR gate from 2:1 MUX: Assumptions: 's' is the select line for the mux. 'I0 and I1' be the input data li…
Verification
Verification and Testing
Verification: In order to verify the functional correctness of a design, one needs to capture the model of the behavior…
Testing
Load and stress testing.
One of the most common, but unfortunate misuse of terminology is treating "load testing" and "stress tes…
Metastability
Digital Logic Metastability Definitions
read further on.... http://www.interfacebus.com/Design_MetaStable.html
Timing
Max Frequency calculation
In the simplest form: FF1 - combo - FF2 ( this is how things look physically for our consideration) Tmin = Tclk2Q (F…
Timing
Ways to increase frequency of operation
Check critical path and optimize it. Add more timing constraints (over constrain). pipeline the architecture to the max…
Formal Verification
When are DFT and Formal verification used?
DFT: manufacturing defects like stuck at "0" or "1". test for set of rules followed during the init…
Gated clocks
Adv and DisAdv of Gated Clocks
Advantges: used to save power by masking the clock to the flops. used in clock switching circuits. Reduces routing burd…
Setup
Setup and Hold times
The setup time is the time the data inputs must be valid before the clock/strobe signal. tSU(chip-pin)= tSU(FF) - Tdela…
Wire load
Wire load models
Wire loading models contain all the information required by compile to estimate interconnect wiring delays. A typical W…
Why
Why interrupts are active low?
What interrupts are active low in digital circuits? In digital circuits, an interrupt is a signal that causes the proce…
Slack
Slack
slack is defined as the difference between the reqd_arrival time of a signal & it's actual arrival time. It sho…
Poleysilicon
Polysilicon Vs Metal
Normally polysilicon has more resistance compared to metal. For shorter distance we go with polysilicon keeping fabrica…
Nor
NAND or NOR design
NAND is a better gate for design than NOR because at the transistor level the mobility of electrons is normally three t…
FPGA
FPGA & ASIC based design
The main diferrence between ASIC and FPGA based design is in the Back-end. In FPGAs there is not much activities in bac…
False Path
Default paths and False paths
The path in digital circuits which is not associated with a clock, is known as default path. While considering and calc…
FPGA
Coarse and Fine grained architectures
Coarse-grained architectures consist of fairly large logic blocks, often containing two or more look-up tables and two …
RTL
Latch Vs Flip Flop
A latch and a flip-flop are two basic building blocks in digital electronics used to store binary data. The main differ…