Showing posts from September, 2008
Archive: September 2008
ASIC Design
This is how you can get a free link to your blog. If you are not already a member of the ASIC/VLSI/Digital Electronics blogging community, join it now! Then write a post in your blog with at least 2 paragraphs and add an active link to this blog below (homepage or individual post page, ie., permalink). When you are done, comment in this post giving the link to the post and we will link to your blog. You can write anything. You can praise us, jus…
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Murugavel Ganesan
September 30, 2008
Semiconductor Industry
According to IC insights , the maket forecast looks grim for 2008 total worldwide IC market growth, noting shrinking demand from fabless suppliers, a weak memory market, and pricing issues that continue to plague the semiconductor industry. After yesterday's failure of US$700B bailout vote in the US house, it looks even more grim to note that spending will reduce drastically against most weak currencies which includes emerging markets. Thank…
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Murugavel Ganesan
September 30, 2008
Verilog
An XVGA (more often called XGA) 1024x768 controller is a pair of counters and a few comparators. At 60 Hz with a 65 MHz pixel clock, a horizontal counter runs from 0 to 1343 and a vertical counter from 0 to 805; comparators on those counts switch the blanking signals and the active-low horizontal and vertical sync pulses at fixed positions. Anything that draws pixels then reads the counters and drives the RGB outputs during the visible 1024 by 7…
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Murugavel Ganesan
September 29, 2008
Opinion
Coaching Excellence in IC Design Teams: Why Can't we get Rid of that Thorn in our Process? Commenting on this article by Jorvig... It is really true. In the past and including the current one i work for all suffer from the same problem. Its ironic that there is no solution in sight but i am sure somebody is reading this article and kicks a thought process to even look at it unless he isn't even aware of it.
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Murugavel Ganesan
September 29, 2008
Jobs
Infineon India - Bangalore is planning for a Fresher's Event in September 08 & thereby invites CVs of friends whose association with the software industry have just begun and would like to be a part of the growing Infineon family for taking up more challenging assignments. Please note that the below mentioned criteria need to be met for a CV to be short listed: The candidate should have 6 months to 2 yrs. of work experience on C Programm…
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Murugavel Ganesan
September 24, 2008
Low Power Design
This classic VLSI and computer architecture interview question asks whether three marketing metrics, MIPS/mm 2 , MIPS/Watt and Watts/cm 3 , are sensible for customers choosing a system. The short answer: MIPS/Watt is reasonable (bigger is better, most relevant to cell phones), Watts/cm 3 is reasonable (smaller is better, most relevant to compute servers), and MIPS/mm 2 is mainly a designer's metric rather than a customer's one. The int…
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Murugavel Ganesan
September 17, 2008
Low Power Design
Your task is to do the power analysis for a circuit that should send out a one-clock-cycle pulse once every 16 clock cycles. (That is, the output is '0' for 15 clock cycles, then '1' for one cycle, then repeat with 15 cycles of '0' followed by a '1', etc.) You have been asked to consider three different types of counters: a binary counter, a Gray-code counter, and a one-hot counter. (The table below shows the va…
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Murugavel Ganesan
September 17, 2008
RTL Design
Your manager has given you the task of implementing the following pseudo code in an FPGA: if is_odd(a + d) { p = (a + d)*2 + ((b + c) - 1)/4; } else { p = (b + c)*2 + d; } NOTES: You must use registers on all input and output ports. p, a, b, c, and d are to be implemented as 8-bit signed signals. A 2-input 8-bit ALU that supports both addition and subtraction takes 1clock cycle. A 2-input 8-bit multiplier or divider takes 4 clock cycles. …
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Murugavel Ganesan
September 17, 2008
Verilog
To compute the greatest common divisor (GCD) of two numbers in hardware, you apply Euclid's algorithm one step per clock cycle: either subtract the smaller value from the larger, or replace the pair (a, b) with (b, a mod b), until one value reaches zero or both are equal. The value left is the GCD. This post explains the algorithm, keeps the original 2008 Verilog example, explains why that code does not compile as written, and gives a correc…
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Murugavel Ganesan
September 16, 2008
Verilog
By Popular Demand! module sqrt (clk,data,start,answer,done); input clk,start; input [7:0] data; output [3:0] answer; output done; reg [3:0] answer; reg busy; reg [1:0] bit; wire [3:0] trial; assign trial = answer | (1 always @ (posedge clk) begin if (busy) begin if (bit == 0) busy else bit if (trial*trial answer end else if (start) begin busy answer bit end end assign done = ~busy; endmodule
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Murugavel Ganesan
September 16, 2008
Verilog
Did you know this basic gotcha of verilog :-) ? You can use the "*" operator to multiply two numbers: wire [9:0] a,b; wire [19:0] result = a * b; // unsigned multiplication! If you want Verilog to treat your operands as signed two's complement numbers, add the keyword signed to your wire or reg declaration: wire signed [9:0] a,b; wire signed [19:0] result = a * b; // signed multiplication! Remember: unlike addition and subtract…
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Murugavel Ganesan
September 16, 2008
Puzzles
"In The Feynman Lectures on Computation , Richard Feynman poses an interesting little puzzle involving the synchronization of finite state machines acting as generals and soldiers. While he was able to find an answer to the problem, the minimum time solution apparently eluded him, and he ended his description of the puzzle with the following Fermat-like declaration : 'Somebody has actually found a solution with this minimum time. That …
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Murugavel Ganesan
September 16, 2008
Interview Questions
This is a famous interview question just that it has got a makeover! Question: Construct a "divisible-by-3" FSM that accepts a binary number entered one bit at a time, most significant bit first, and indicates with a light if the number entered so far is divisible by 3. Draw a state transition diagram for your FSM indicating the initial state and for which states the light should be turned on. Hint: the FSM has 3 states…
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Murugavel Ganesan
September 15, 2008
Puzzles
Hello All: In fact it has been a long time since we had posted any sort of interview questions or puzzles and so here we are with a very practical problem. Lets see how many of you can crack it! I will post the solutions depending on the responses. Thanks. The problem: The Sheel lock Company has recently received an order from Mr. Manmohan Singh for their all-digital Perfectly Perplexing Padlock(P3). The P3 has two buttons ("0"…
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Murugavel Ganesan
September 15, 2008
Semiconductor Industry
Hello & Best wishes! Due to overwhelming responses to this Blog and successful placement of 500+ Freshers and experienced professionals alike, after requests for Job guidance through Emails and Messages we have decided to evolve the career branch (http://vlsi-jobs.blogspot.com) of The Digital Electronics Blog. You support and patronage is highly essential and as usual this service is planned to be absolutely free with help from sponsors. Ple…
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Murugavel Ganesan
September 05, 2008
